Iterative architecture for hierarchical scheduling

Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Prioritized data routing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C709S230000, C709S232000, C709S233000, C709S234000

Reexamination Certificate

active

07321940

ABSTRACT:
Conventional schedulers employ designs allocating specific processor and memory resources, such as memory for configuration data, state data, and scheduling engine processor resources for specific aspects of the scheduler, such as layers of the scheduling hierarchy, each of which consumes dedicated processor and memory resources. A generic, iterative scheduling engine, applicable to an arbitrary scheduling hierarchy structure having a variable number of hierarchy layers, receives a scheduling hierarchy structure having a predetermined number of layers, and allocates scheduling resources such as instructions and memory, according to scheduling logic, in response to design constraints and processing considerations. The resulting scheduling logic processes the scheduling hierarchy in iterative manner which allocates the available resources among the layers of the hierarchy, such that the scheduler achieves throughput requirements corresponding to enqueue and dequeue events with consideration to the number of layers in the scheduling hierarchy and the corresponding granularity of queuing.

REFERENCES:
patent: 6016399 (2000-01-01), Chang
patent: 6072772 (2000-06-01), Charny et al.
patent: 6236413 (2001-05-01), Gossett et al.
patent: 6263430 (2001-07-01), Trimberger et al.
patent: 6487213 (2002-11-01), Chao
patent: 6519595 (2003-02-01), Rose
patent: 6667984 (2003-12-01), Chao et al.
patent: 6714553 (2004-03-01), Poole et al.
patent: 6738346 (2004-05-01), Prieto et al.
patent: 6747976 (2004-06-01), Bensaou et al.
patent: 6865154 (2005-03-01), Charny et al.
patent: 7027457 (2006-04-01), Chiussi et al.
patent: 2002/0073226 (2002-06-01), Sridhar et al.
patent: 2002/0101822 (2002-08-01), Ayyagari et al.
patent: 2002/0118683 (2002-08-01), Narayana et al.
patent: 2002/0122422 (2002-09-01), Kenney et al.
patent: 2002/0126690 (2002-09-01), Narayana et al.
patent: 2002/0176431 (2002-11-01), Golla et al.
patent: 2003/0021266 (2003-01-01), Oki et al.
patent: 2003/0033039 (2003-02-01), Gutberlet et al.
patent: 2004/0013089 (2004-01-01), Taneja et al.
patent: 2004/0064678 (2004-04-01), Black et al.
patent: 2004/0081167 (2004-04-01), Hassan-Ali et al.
patent: 2004/0264500 (2004-12-01), Bansal et al.
patent: 2005/0177644 (2005-08-01), Basso et al.
McKeown et al. The iSLIP Scheduling Algorithm for Input-Queued Switches, http:/
ms.csail.mit.edu/6829-papers/islip-ton.pdf, 1999.
Kim et al. Hierarchical scheduling algorithm for QoS guarantee in MIQ switches. http://ieeexplore.ieee.org/iel5/2220/18791/00868134.pdf?arnumber=868134.
Anderson et al. High speed switch scheduling for LANs. http://delivery.acm.org/10.1145/150000/143495/p98-anderson.pdf?key1=143495&key2=9272946711&coll=portal&dl=ACM&CFID=19890684&CFTOKEN=29677744.
McKeown et al. The iSLIP Scheduling Algorithm for Input-Queued Switches, http:/
ms.csail.mit.edu/6829-papers/islip-ton.pdf, 1999.
McKeown et al. The iSLIP Scheduling Algorithm for Input-Queued Switches, http:/
ms.csail.mit.edu/6829-papers/islip-ton.pdf, 1999.
Kim et al. Hierarchical scheduling algorithm for QoS guarantee in MIQ switches. http://ieeexplore.ieee.org/iel5/2220/18791/00868134.pdf?arnumber=868134. Aug. 31, 2000.
Anderson et al. High speed switch scheduling for LANs. http://delivery.acm.org/10.1145/150000/143495/p98-anderson.pdf?key1=143495&key2=9272946711&coll=portal&dl=ACM&CFID=19890684&CFTOKEN=29677744. 1992.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Iterative architecture for hierarchical scheduling does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Iterative architecture for hierarchical scheduling, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Iterative architecture for hierarchical scheduling will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3962362

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.