Iterative abstraction using SAT-based BMC with proof analysis

Details Iterative abstraction using SAT-based BMC with proof analysis Iterative abstraction using SAT-based BMC with proof analysis

2004-01-23

2010-06-22

Rodriguez, Paul L (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C716S030000

Reexamination Certificate

active

07742907

ABSTRACT:
A method of obtaining a resolution-based proof of unsatisfiability using a SAT procedure for a hybrid Boolean constraint problem comprising representing constraints as a combination of clauses and interconnected gates. The proof is obtained as a combination of clauses, circuit gates and gate connectivity constraints sufficient for unsatisfiability.

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