Isotropic dry cleaning process for noble metal integrated...

Etching a substrate: processes – Forming or treating electrical conductor article

Reexamination Certificate

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C216S067000, C134S001100, C438S906000, C252S079100

Reexamination Certificate

active

06254792

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an isotropic dry cleaning process for noble metal integrated circuit structures.
2. Description of the Related Art
Thin films of noble metals (Pt, Pd, Ir, Rh) have become technologically important in integrated circuits (ICs) as electrodes for ferroelectric and high &egr; thin films in FeRAMs, DRAMs, RF and microwave MMICs, pyroelectric IR focal plane detector arrays, etc.
The absence of viable dry etching techniques for submicron patterning of these electrodes is a chronic problem that has threatened to retard or even prevent widespread use of these materials. The present dry-etching approaches utilize plasmas for reactive ion etching (RIE), are chlorine-based, and result in significant residue being left on the microelectronic device structure after the etch process has been completed.
Depending on the type of structure that is being formed by the patterning, this post-etch residue may result in short circuiting, undesired topography or other deficiencies in the operation of the circuit element in subsequent use of the product microelectronic device. Prevention of the formation of such residues may be achieved in some instances by manipulating the reactive ion etching (RIE) process parameters, but such process manipulation results in undesirable sidewall slopes in the microelectronic device structure that effectively prevent useful submicron capacitors from being fabricated.
Alternatively, the residue resulting from RIE can be removed by wet rinsing techniques, after the etch process has been completed. Wet rinsing techniques are however generally unsatisfactory, because a significant fraction of the residue may be transported in suspension in the rinse media, allowing a small fraction of the residue solids to redeposit on the wafer, and thereby reducing device yield.
Further, in some microelectronic device structure geometries, the residue may not be removed using wet rinsing methods.
Another drawback of wet rinsing methods is the need for a separate process tool to implement the wet rinsing clean-up, which adds to the capital equipment and operating costs of the process system.
It would therefore be a significant advance in the art of integrated circuit device fabrication, in which noble metal films are formed on the device substrate as electrodes or other structural components of the device, to provide an effective cleaning process for removing unwanted residues on the integrated circuit structure after etching or other process fabrication steps.
SUMMARY OF THE INVENTION
The present invention relates to a method for removing noble metal residue from a microelectronic device structure during the fabrication thereof, by contacting the microelectronic device structure with a gas-phase reactive halide composition, e.g., XeF
2
, SF
6
, Si
2
F
6
, SiF
4
, or SiF
2
and/or SiF
3
radicals, for sufficient time and under sufficient conditions to at least partially remove the noble metal residue.
Such “dry clean” method of the invention effects an isotropic dry etching of the noble metal residue for removal thereof. The isotropic dry etching is carried out under low-pressure exposure of the noble metal residue to the reactive halide gas.
The reactive halide may comprise any suitable halide substituent, e.g., fluorine, bromine, chlorine, or iodine, with fluorine generally being most preferred. The reactive halide agent may itself comprise the reaction product of an initial reaction, such as the reaction of XeF
2
with silicon to form SiF
2
and/or SiF
3
radicals as the reactive halide agent. In this manner SF
6
, SiF
4
or Si
2
F
6
may be used with an activation source (ion beam, electron beam, ultra violet or laser) to produce the reactive radical species.
The invention contemplates two main cleaning techniques for using the reactive halide gas as an isotropic noble metal etch agent to remove residual noble metal deposits from the microelectronic device structure.
The first technique is a batch contacting method wherein a chamber containing the microelectronic device structure is evacuated and backfilled with the reactive halide gas or a mixture of the reactive halide gas and other gas(es), either inert or reactive. After the reactive halide is allowed to react for a predetermined amount of time, the chamber is evacuated and backfilled again with fresh cleaning gas. The evacuation pressure can be less than or equal to 50 mTorr. The backfill pressure can be from about 50 mTorr to about 2 Torr, the exposure time can be from about 10 seconds to about 10 min, and the number of exposure cycles is not limited, but will depend on the amount of material to be removed.
The second technique using the reactive halide gas as an isotropic etch agent is a continuous gas flow method. In this technique, a steady state flow of the reactive halide gas, e.g., XeF
2
, SF
6
, Si
2
F
6
or SiF
4
, is introduced to the chamber containing the microelectronic device structure to be cleaned. Either pure reactive halide gas or a mixture of the reactive halide and other gas(es), either inert or reactive, may be used. The partial pressure of the reactive halide gas can be from about 50 mTorr to about 2 Torr and total flow rate of the reactive halide gas can be from about 1 standard cubic centimeter per minute (sccm) to about 10 standard liters per minute (slm).
In either case of batch or continuous operation, the microelectronic device structure to be cleaned may be held at temperatures in the range of from about −50° C. to about 200° C.
In the foregoing methodology, the reactive halide gas may for example comprise a XeF
2
vapor. Such vapor may be obtained from the sublimation of XeF
2
solid crystals. XeF
2
will sublime at room temperature, but may be heated to increase the rate of sublimation.
Additionally, the XeF
2
may first be reacted with elemental silicon, and the resultant reaction product used as the etching gas. It is known that XeF
2
etches silicon to produce SiF
4
Si
2
F
6
and SiF
2
and SiF
3
radicals.
The reactive halide composition may also be produced in an upstream plasma, e.g., SiF
2
and SiF
3
radicals may be formed by passing SiF
4
gas through a remote plasma.
The method of the invention is usefully employed for removal of noble metal residues comprising Ir, Rh, Pd and/or Pt, and may be utilized for cleaning hybrid electrodes comprising alloys or combinations of such metals, as well as alloys or combinations of one or more of such metals with other (non-noble) metals.
Other aspects, features and embodiments of the invention will be more fully apparent from the ensuing disclosure and appended claims.


REFERENCES:
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patent: 5814238 (1998-09-01), Ashby et al.
patent: 5911887 (1999-06-01), Smith et al.
patent: 6018065 (2000-01-01), Baum et al.
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Jeon, et al., “Thermal Stability of Ir/Polycrystalline-Si Structure for Bottom Electrode of Integrated Ferroelectric Capacitors”,Appl. Physics Lett., 1997, vol. 71(4), pp. 467-469.
Williams, et al., “Etch Rates for Micromachining Processing”,Journ. For Microelectromechanical Systems, Dec. 1996, vol. 5 (4), pp. 256-269.
Vugts, et al., “Si/XeF2Etching-Temperature Dependence”, 1996,J. Vac. Sci. Tech. A, vol. 14(5), pp. 2766-2774.
P.C. Fazan, et al., “Stacked Capacitor Modules for 64 Mb DRAMs and Beyond”,Semiconductor Inter., 1992, vol. 108, pp. 108-112.
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R. E. Sievers, et al., “Volatile Barium B-Diketonates for Use as MOCVD Precursors”,Coord. Chem. Rev., 1993, pp. 285-291.
C. Farrell, et al., “A Reactive Ion Etch Study for Producing Patterned Platinum Structures”, Presented at ISIF 96, Mar. 18,19,20, 1996 Tempe AZ. (to be published in Integrated Ferroelectrics).
K. R. Milkove and C. X, Wang, “Insight into the dry cleaning of Fence Patterned Platinum Sturctures”,J. Vac. Sci. Tech.

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