Isolation trenches for memory devices

Details Isolation trenches for memory devices Isolation trenches for memory devices

2005-05-16

2008-10-21

Gurley, Lynne A. (Department: 2811)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S201000, C438S257000, C438S258000, C438S259000, C438S260000, C438S261000, C438S262000, C438S263000, C438S264000, C438S265000, C438S266000, C438S267000, C257SE21680

Reexamination Certificate

active

07439157

ABSTRACT:
A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric layer containing a different dielectric material than the first dielectric layer; depositing a third dielectric layer to fill the trench; removing an upper portion of the third dielectric layer from the trench and leaving a lower portion covering a portion of the second dielectric layer; oxidizing the lower portion of the third dielectric layer after removing the upper portion; removing an exposed portion of the second dielectric layer from the trench, thereby exposing a portion of the first dielectric layer; and forming a fourth dielectric layer in the trench covering the exposed portion of the first dielectric layer.

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S.H. Shin et al.; Data Retention Time and Electrical Characteristics of Cell Transistor According to STI Materials in 90nm DRAM; Journal of Semiconductor Technology and Science; vol. 3, No. 2; Jun. 2003; pp. 69-75.
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