Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2011-02-22
2011-02-22
Hu, Shouxiang (Department: 2811)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S201000, C438S257000, C438S258000, C438S260000, C438S261000, C438S262000, C438S263000, C438S264000, C438S265000, C438S266000, C438S267000, C438S314000, C438S315000, C438S316000, C438S317000, C438S319000, C438S320000, C257SE21680
Reexamination Certificate
active
07892943
ABSTRACT:
A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.
REFERENCES:
patent: 6265281 (2001-07-01), Reinberg
patent: 6322634 (2001-11-01), Pan
patent: 6437417 (2002-08-01), Gilton
patent: 6566229 (2003-05-01), Hong
patent: 6596607 (2003-07-01), Ahn
patent: 6627529 (2003-09-01), Ireland
patent: 6693050 (2004-02-01), Cui
patent: 6756654 (2004-06-01), Heo et al.
patent: 6780721 (2004-08-01), Farrar
patent: 6897120 (2005-05-01), Trapp
patent: 7033909 (2006-04-01), Kim et al.
patent: 7105397 (2006-09-01), Hieda et al.
patent: 7208812 (2007-04-01), Ohta
patent: 7332408 (2008-02-01), Violette
patent: 2002/0072198 (2002-06-01), Ahn
patent: 2002/0127817 (2002-09-01), Heo et al.
patent: 2003/0006476 (2003-01-01), Chen et al.
patent: 2003/0013271 (2003-01-01), Knorr et al.
patent: 2003/0143852 (2003-07-01), En-Ho et al.
patent: 2004/0072408 (2004-04-01), Yun et al.
patent: 2004/0192009 (2004-09-01), Belyansky et al.
patent: 2005/0287731 (2005-12-01), Bian et al.
patent: 2006/0255426 (2006-11-01), Inoue et al.
S.H. Shin, et al., “Data Retention Time and Electrical Characteristics of Cell Transfer According to STI Materials in 90 nm DRAM,” Journal of Semiconductor Technology and Science, vol. 3, No. 2, Jun. 2003, pp. 69-75.
Sukesh Sandhu, “Method for Filling Shallow Isolation Trenches and Other Recesses During the Formation of a Semiconductor Device and Electronic Systems Including the Semiconductor Device,” (24 pages including drawings) U.S. Appl. No. 11/371,680, filed Mar. 8, 2006.
Gebremariam Samuel A
Hu Shouxiang
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
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