Isolation trench structure for integrated devices

Details Isolation trench structure for integrated devices Isolation trench structure for integrated devices

2001-05-10

2004-09-28

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S520000

Reexamination Certificate

active

06798037

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an integrated device having an isolation structure.
Specifically, the invention relates to an integrated device of a type that has a substrate, wherein a buried layer and an epitaxial region have been formed, and includes an isolation structure effectively defining a number of isolation wells for integrating the components of the integrated device therein. The invention also relates to a process for fabricating the above integrated device with an isolation structure.
BACKGROUND OF THE INVENTION
As is known, in most semiconductor-integrated devices, the integrated components are isolated electrically using a technique referred to as junction isolation.
FIG. 1
is a vertical cross-section showing schematically an integrated device IC with conventional isolation structures. In particular, that integrated device IC includes wells A, which are doped with a first dopant type (N-type, in this instance) and intended to receive components of various description. The components may be bipolar and/or MOS types, for example.
The wells A are bordered by an isolation region B, doped with a second dopant type (P-type, in this instance). Thus, the wells A are isolated electrically by reverse biasing the P-N junctions defined by the wells A and the isolation region B. This is known as “junction isolation”.
The effectiveness of junction isolation depends on the kind of components integrated in the wells A, as well as on the kind of circuitry that comprises the integrated device IC.
It should be considered, however, that the reverse bias condition of the P-N junctions defined by the wells A and the isolation region B can not always be maintained through different circumstances of the integrated device operation. Also, capacitive and/or inductive effects, due either to the presence of several layers or the type of the bias applied, make the electrical isolation of the integrated components in the wells A by the junction isolation method uncertain.
Furthermore, the latter method uses up a large silicon area. In fact, the area occupied by an active component of a type whichever, integrated in a well A, is much smaller than that occupied by the isolation region B, the latter encompassing deep layers of considerable spread.
There are known basically two technologies for fabricating an integrated device with a conventional junction isolation structure.
With a so-called low-power technology, shown schematically in
FIG. 2
, masking, implanting, and N-dopant diffusing steps are carried out on a P-type semiconductor material (substrate
1
) to produce a buried layer
2
of the N
+
type. In particular, the buried layer
2
represents the collector or the drain region of an NPN bipolar or a VDMOS component, respectively.
An N-type epitaxial region
3
is then grown, which is followed by masking, implanting, and P-dopant diffusing steps carried out to produce isolation regions
4
effectively providing sidewall insulation for the isolation wells IS defined by the epitaxial region
3
and the buried layer
2
.
Subsequent masking, implanting, and N-dopant diffusing steps produce sinker regions
5
at the ends of the buried layer
2
. These sinker regions
5
establish contact between the surface of the integrated device IC and the buried layer
2
.
Additional layers, such as P-well and N-well regions, active areas, etc., are then integrated in the N-type isolation wells IS bordered by P-doped regions, in particular the substrate
1
and isolation region
4
, as required to complete different components.
Defining surface-enhancement regions and contact areas, and a metallizing and passivating step, close the process of fabricating the integrated device IC.
With a VIPower technology, shown in
FIG. 3
, the vertical current flow power components, e.g., VIPower devices, comprise an N-type substrate.
The process sequence that leads to an integrated device IC being defined with junction isolation wells IS. starts with a semiconductor material
1
of the N
+
type and comprises an initial step of forming a first epitaxial region
11
of the N
+
type, followed by a masking, implanting, and P-dopant diffusing step to form a buried layer
12
of the isolation well.
In particular, the buried layer
12
, additionally to providing part of the buried insulator for the drive circuitry or region LV, provides here part of the base region of the NPN power component or region IIV.
A subsequent masking, implanting, and N-dopant diffusing step, carried out at the buried layer
12
, will bulk delimit the N-type regions
2
intended to contain various circuitry components, as described in connection with the prior art shown in FIG.
1
.
The buried layer
12
, besides providing the emitter for the NPN power component in the region HV, also functions as a buried collector and buried drain for the NPN and VDMOS signal components, respectively, in the region LV.
An additional epitaxial region
3
is necessary to provide N-type isolated wells IS, These wells are fully delimited with an additional masking, implanting, and P-type diffusing step to form the isolation regions
4
in the epitaxial region
3
and ensure electrical continuity to the buried region
12
.
The isolation regions
4
are also part of the base of the NPN bipolar power component.
Once the isolation regions
4
are defined, a subsequent masking, implanting, and N-dopant diffusing step will provide the sinker regions
5
at the ends of the buried layer
2
, thereby placing the surface of the integrated device IC in contact with the buried layer
2
.
On completion of the above steps, other layers will be integrated in the N-type isolation wells IS comprising the buried layer
2
and the epitaxial region
3
, to form various components, e.g., P-well and N-well regions, active areas, etc.
The fabrication of the integrated device IC is completed with the definition of surface enhancement regions, contact areas, and the associated metallizing and passivating step.
Note should be taken that the above conventional isolation well structures IS closely resemble each other. The only differences to be seen are in the substrate, of the P type or the N type, and the integration of the region
12
with VIPower technology.
SUMMARY OF THE INVENTION
The disclosed embodiments of the invention provide an integrated device with an isolation structure of the dielectric kind, which device has reduced area requirements and improved electrical isolation of the integrated components in the isolation wells, the space requirements of the isolation structure being also reduced, and the isolation structure suiting any (low- and high-voltage) semiconductor devices provided with isolation wells that have been formed by the junction isolation technique.
An integrated device with an isolation structure is provided that includes dielectric trench regions to ensure sidewall insulation of the components, which dielectric trench regions are filled with a conductive material in order to have the buried regions contacted from the surface.
In accordance with another aspect of the invention, an integrated device with an isolation structure is provided, including a substrate having a buried layer and an epitaxial region, the isolation structure adapted to define a plurality of isolation wells for integrating the components of the integrated device formed therein. The isolation structure includes plural dielectrically insulated trenches filled with a conductive material to form a plurality of contact regions to buried regions of the device, the buried regions including the substrate and the buried layer. Preferably, the dielectric trenches are formed at the edges of the isolation wells in contact with the buried layer. Ideally, the trenches each comprise thick dielectric regions surrounding a contact region.
In accordance with another aspect of the invention, a process for fabricating an integrated device having an isolation structure is provided that includes doping a substrate with a first dopant type; masking the substrate, implanting and defu

Affiliated with

Also associated with

Rating

Isolation trench structure for integrated devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Isolation trench structure for integrated devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Isolation trench structure for integrated devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3272845