Isolation trench fill process

Details Isolation trench fill process Isolation trench fill process

2002-04-09

2004-10-19

Blum, David S (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

Reexamination Certificate

active

06806165

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor processing, and more particularly to a method for filling isolation trenches during semiconductor processing.
BACKGROUND OF THE INVENTION
During the fabrication of semiconductor devices, isolation trenches are provided between active areas where transistors will be located. The trenches extend into a silicon substrate and are filled with an insulating material, such as oxide, to form lines of oxide insulating regions. As the aspect-ratio for the isolation trench structure increases, it becomes increasingly more difficult to fill the trench without forming voids in the oxide near the center of the trench. The consistency of void-free gap fill has a significant effect on the subsequent integration process steps and on final device yield and performance.
Current techniques for gap filling the isolation trenches utilize a high density plasma (“HDP”) deposition technique to produce a high-quality oxide filler. With HDP processing, high-aspect-ratio sub-half micron structures can be filled and locally planarized in a single processing step. Generally, ions and electrons from the plasma are generated at an electrode by means of an RF biasing power, and an RF power source is applied to another electrode (located at a holder for a wafer) to create a significant ion bombardment (sputter-etching) component during deposition. Thus, gap filling using HDP is a simultaneous deposition/etching process. This process allows trench isolation structures with high-aspect-ratios to be filled with high-quality oxide dielectric.
While HDP deposition of the oxide has been found to produce a high-quality void-free gap fill, it has been observed that deposition of the oxide is not uniform and, in some circumstances, completely lacking in some portions of the isolation trench line. This observed defect is illustrated in
FIGS. 1A
,
1
B and
1
C.
FIG. 1A
illustrates a view looking down onto the substrate surface
10
. One of a plurality of isolation trench lines
24
a
is illustrated after the HDP oxide
30
has been deposited and polished back. The defect
40
is an unfilled area of the isolation trench
24
a
.
FIGS. 1B and 1C
illustrate cross-sectional views of the defect
40
at A—A, and B—B, respectively. As is shown in
FIGS. 1B and 1C
, the unfilled pockets occur at the isolation trench surface
50
(
FIG. 1B
) and can grow to encompass the entire isolation trench
24
a
(FIG.
1
C). This defect
40
can significantly effect final device yield and performance.
Accordingly what is needed is an improved isolation trench fill process that produces a defect-free insulating layer. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method for filling an isolation trench structure during a semiconductor fabrication process. The method includes a two-step deposition process that includes depositing a silicon-rich liner on the trench surface, and thereafter, filling the isolation trenches with an oxide utilizing a biased high density plasma deposition process. In a preferred embodiment, the silicon-rich liner is an in-situ HDP liner having a thickness of approximately 200 Angstroms.
According to the method disclosed herein, depositing a silicon-rich liner on the trench surface prior to depositing the high density plasma oxide eliminates the formation of bubbles at the surface of the isolation trench structure. Thus, the quality of the oxide fill is improved, as is yield and device performance.


REFERENCES:
patent: 6187651 (2001-02-01), Oh
patent: 6228742 (2001-05-01), Yew et al.
patent: 6297128 (2001-10-01), Kim et al.
patent: 6326282 (2001-12-01), Park et al.
patent: 6441426 (2002-08-01), Fukumoto et al.
Stanley Wolf Silicon Processing for the VSLI ERA vol. 1 Lattice Press 2000 pp. 795-796.*
Stanley Wolf Silicon Processing for the VSLI ERA vol. 1 Lattice Press 1986 pp. 171-173 and 191-193.*
John Vossen Thin Film Processing Academic Press 1978 p. 54.

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