Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2003-05-12
2011-10-04
Malsawma, Lex (Department: 2892)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C257SE21546
Reexamination Certificate
active
08030172
ABSTRACT:
A semiconductor structure has a substrate having a trench, an isolation dielectric in the trench, and a stress buffer layer, between the substrate and the dielectric. Semiconductor devices containing the semiconductor structure may have higher reliability, and may have a reduced manufacturing costs per device.
REFERENCES:
patent: 4631803 (1986-12-01), Hunter et al.
patent: 4789648 (1988-12-01), Chow et al.
patent: 4851662 (1989-07-01), Ott et al.
patent: 4870470 (1989-09-01), Bass et al.
patent: 4954142 (1990-09-01), Carr et al.
patent: 5262354 (1993-11-01), Cote et al.
patent: 5447884 (1995-09-01), Fahey et al.
patent: 5943599 (1999-08-01), Yao et al.
patent: 6022776 (2000-02-01), Lien et al.
patent: 6159823 (2000-12-01), Song et al.
patent: 6165854 (2000-12-01), Wu
patent: 6326282 (2001-12-01), Park et al.
patent: 6333242 (2001-12-01), Hwang et al.
patent: 6465373 (2002-10-01), Zheng et al.
patent: 6596654 (2003-07-01), Bayman et al.
patent: 6867086 (2005-03-01), Chen et al.
patent: 2002/0068416 (2002-06-01), Hsieh et al.
patent: 2002/0076917 (2002-06-01), Barth et al.
Omar et al., “The Effect of Backside Films on Rapid Thermal Oxidation (RTO) Growth on Silicon Wafers”, ICSE'98 Proc., Nov. 1998, pp. 81-85.
Encyclopedia of Chemical Technology, Kirk-Othmer, vol. 14, pp. 677-709 (1995).
Pearson, G.L., et al., “Deformation and Fracture of Small Silicon Crystals,”Acta Metallurgica, vol. 5, 1957, pp. 181-191.
Runyan, W.R., “Elastic Constants,” Silicon Semiconductor Technology, Texas Instruments Electronics Series, McGraw-Hill Book Company, 1965, pp. 216-218.
Microchip Fabrication: A Practical Guide to Semiconductor Processing, 3rd. edition, Peter Van Zant, McGraw-Hill, Chapter 16, pp. 491-527 (2000).
Visser, C.C.G., et al., “A New Silicon Nitride Mask Technology for Synchrotron Radiation X-Ray Lithography: First Results,”Micro Electronic Engineering6, 1987, pp. 299-303.
Pierret, Robert F., “Semiconductor Device Fundamentals”, p. 4, Table 1.1, Addison-Wesley, 1996.
Ahn Yongchul
Jayatilaka Venuka
Wong Kaichiu
Cypress Semiconductor Corporation
Malsawma Lex
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