Isolation technology for sub-micron devices

Details Isolation technology for sub-micron devices Isolation technology for sub-micron devices

1994-05-24

1995-12-05

Fourson, George

Fishing, trapping, and vermin destroying

437 72, 437968, H01L 2176

Patent

active

054729033

ABSTRACT:
A new isolation technology fabrication process is provided including the step of forming a trench in a semiconductor material. Then, several poly walls are formed in the trench. The poly walls are oxidized to form a single oxide isolation region filling the trench.

REFERENCES:
patent: 4666556 (1987-05-01), Fulton et al.
Kurosawa et al., A New Bird's -Beak Free Field Isolation for VLSI Devices, International Electron Devices Meeting, Dig. Tech, Paper, pp. 384-387 (1981).
Rung et al., Deep Trench Isolated CMOS Devices, International Electron Devices Meeting, Digest Technical Paper, pp. 237-240 (1982).
Katsumata et al., Sub-20 ps ECL Bipolar Technology with High Breakdown Voltage, ESSDERC (Sep. 1993).
Lutze et al., Electrical Limitations of Advanced LOCOS Isolation for Deep Submicrometer CMOS, IEEE Transactions on Electron Devices, vol. 38, No. 2 (Feb., 1991).
Poon et al., A Trench Isolation Process for BiCMOS Circuits, IEEE Bipolar Circuits and Technology Meeting 3.3 (1993).

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