Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2007-10-09
2007-10-09
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S513000, C257S520000, C257S223000, C257S230000, C257S292000, C257S523000, C257SE27139, C257SE27145
Reexamination Certificate
active
11141387
ABSTRACT:
A structure for isolating areas in a semiconductor device is provided. The structure includes a trench having first and second portions formed in a substrate. The first portion has a first width, and the second portion has a second width and is below the first portion. The first width is greater than the second width. A first insulating liner is formed along at least lateral sidewalls of the first portion. A spacer material is formed along at least lateral sidewalls of the insulating liner and filling the second portion. A filler material is over said spacer material and within the first portion. Methods for forming the structure are also provided.
REFERENCES:
patent: 4528047 (1985-07-01), Beyer et al.
patent: 4820654 (1989-04-01), Lee
patent: 4965217 (1990-10-01), Desilets et al.
patent: 5087586 (1992-02-01), Chan et al.
patent: 6118142 (2000-09-01), Chen et al.
patent: 6177333 (2001-01-01), Rhodes
patent: 6204524 (2001-03-01), Rhodes
patent: 6232626 (2001-05-01), Rhodes
patent: 6235610 (2001-05-01), Nicotra et al.
patent: 6404000 (2002-06-01), Divakaruni et al.
patent: 6483163 (2002-11-01), Isogai et al.
patent: 6501149 (2002-12-01), Hong
patent: 6518641 (2003-02-01), Mandelman et al.
patent: 6545302 (2003-04-01), Han
patent: 6548861 (2003-04-01), Palm et al.
patent: 6555891 (2003-04-01), Furukawa et al.
patent: 6723618 (2004-04-01), Meyer et al.
patent: 6911367 (2005-06-01), Blomiley et al.
patent: 2002/0158281 (2002-10-01), Golbach et al.
patent: 2003/0071321 (2003-04-01), Hong
patent: 2003/0199136 (2003-10-01), Kim et al.
patent: 2004/0038533 (2004-02-01), Liang
patent: 2004/0058549 (2004-03-01), Ho et al.
patent: 2005/0196976 (2005-09-01), Rueger et al.
patent: 2005/0221559 (2005-10-01), Sumino et al.
R. H. Nixon et al.—“256×256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid State Circuits, vol. 31, No. 12, Dec. 1996, pp. 2046-2050.
Sunetra Mendis et al.—“CMOS Active Pixel Image Sensor,” IEEE Transactions on Electron Devices, vol. 41, No. 3, Mar. 1994, pp. 452-453.
Dickstein & Shapiro LLP
Jackson Jerome
Nguyen Joseph
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