Isolation technique for silicon germanium devices

Details Isolation technique for silicon germanium devices Isolation technique for silicon germanium devices

1993-09-01

1994-05-03

Fourson, George

Fishing, trapping, and vermin destroying

437 90, 437 99, H01L 2176

Patent

active

053087852

ABSTRACT:
The present invention is an isolation structure for use with FET or bipolar devices incorporating a silicon-germanium layer in which the semiconductor devices are isolated by trench structures. A trench is etched through a pad layer, a single crystal silicon layer, a silicon-germanium layer, and finally, into the silicon substrate. The silicon-germanium layer is interposed between the single crystal silicon layer and the silicon substrate and the pad layer covers the single crystal silicon layer. The trench sidewall exposes the silicon-germanium layer. A single crystal silicon layer is formed as a trench liner. This silicon trench liner is then oxidized to passivate the trench isolation. The trench can then be filled with a dielectric without the devices being affected by parasitic leakage caused by the silicon-germanium layer exposed by the trench isolation.

REFERENCES:
patent: 4849370 (1989-06-01), Spratt et al.
patent: 4982263 (1991-01-01), Spratt et al.
patent: 4997776 (1991-05-01), Harame et al.
patent: 5114876 (1992-05-01), Weiner
patent: 5202284 (1993-04-01), Karmine et al.
patent: 5212110 (1993-05-01), Pfiester et al.

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