Isolation technique for silicon germanium devices

Details Isolation technique for silicon germanium devices Isolation technique for silicon germanium devices

1992-01-24

1993-11-30

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Heterojunction

257200, 257201, 257616, H01L 3112

Patent

active

052668134

ABSTRACT:
The present invention is an isolation structure for use with FET or bipolar devices incorporating a silicon-germanium layer in which the semiconductor devices are isolated by trench structures. A trench is etched through a pad layer, a single crystal silicon layer, a silicon-germanium layer, and finally, into the silicon substrate. The silicon-germanium layer is interposed between the single crystal silicon layer and the silicon substrate and the pad layer covers the single crystal silicon layer. The trench sidewall exposes the silicon-germanium layer. A single crystal silicon layer is formed as a trench liner. This silicon trench liner is then oxidized to passivate the trench isolation. The trench can then be filled with a dielectric without the devices being affected by parasitic leakage caused by the silicon-germanium layer exposed by the trench isolation.

REFERENCES:
patent: 4771326 (1988-09-01), Curran
patent: 4806996 (1989-02-01), Luryi
patent: 4959694 (1990-09-01), Gell
patent: 5006912 (1991-04-01), Smith
patent: 5019882 (1991-05-01), Solomon
patent: 5155571 (1992-10-01), Wang et al.

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