Isolation structures for imposing stress patterns

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

Reexamination Certificate

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C257S274000, C257S324000, C257S330000, C257S374000, C438S154000

Reexamination Certificate

active

06974981

ABSTRACT:
A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate areas. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance are achieved.

REFERENCES:
patent: 6057581 (2000-05-01), Doan
patent: 6075262 (2000-06-01), Moriuchi et al.
patent: 6258695 (2001-07-01), Dunn et al.
IEDM 2000 “Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design”, Ito et al., NEC Corporation, ppgs 10.7.01-10.7.4.
IEEE Transactions on Electron Devices, vol. 38, No. 4, Apr. 1991, “A new aspect of mechanical stress effects in scaled MOS devices”, Hamada et al. ppgs. 895-900.
2001 Symposium on VLSI Technology Digest of Technical Papers “Strained Si NMOSFETs for high performance CMOS technology”, Rim et al., ppgs. 59-60.
J. Appl. Phys. vol. 70, No. 6, Sep. 15, 1991, “Stress-related problems in silicon technology”, ppgs R53-R80.

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