Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1998-12-14
2001-06-12
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S409000, C257S367000, C257S488000, C257S520000
Reexamination Certificate
active
06246101
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an isolation structure and a semiconductor device including the isolation structure, and more specifically, it relates to an isolation structure capable of suppressing electric field concentration and a semiconductor device including the isolation structure.
2. Description of the Prior Art
In general, a p-channel LIGBT (lateral insulated gate bipolar transistor) formed on an SOI (silicon on insulator) substrate is known as one of semiconductor devices. This LIGBT is a MOS gate controlled power device generally applied to an electric motor or the like requiring a high voltage and a heavy current.
FIG. 51
is a sectional view showing a conventional p-channel LIGBT. With reference to
FIG. 51
, the structure of the conventional p-channel LIGBT is now described.
Referring to
FIG. 51
, the conventional p-channel LIGBT includes a semiconductor substrate
101
, a buried oxide film
102
, an n
−
-type SOI layer
103
, a p-channel MOS transistor
104
, a p
+
-type emitter diffusion region
105
, an n-type emitter diffusion region
106
, a p
−
-type diffusion region
107
, a p-type collector diffusion region
109
, an n
+
-type collector diffusion region
110
, a gate insulator film
108
, a field oxide film
111
a
, first multi-field plates
112
a
to
112
c
, second multi-field plates
114
a
to
114
d
, an emitter electrode
116
and a collector electrode
117
.
The buried oxide film
102
is formed on the semiconductor substrate
101
. The n
−
-type SOI layer
103
is formed on the buried oxide film
102
. The p
+
-type emitter diffusion region
105
, the n-type emitter diffusion region
106
, the p
−
-type diffusion region
107
, the p-type collector diffusion region
109
and the n
+
-type collector diffusion region
110
are formed on prescribed regions of the SOI layer
103
. The field oxide film
111
a
is formed on a major surface of the SOI layer
103
in a region positioned on the p
−
-type diffusion region
107
. The gate insulator film
108
is formed on the major surface of the SOI layer
103
. The gate electrode
120
is formed on the gate insulator film
108
. The p
+
-type emitter diffusion region
105
, the p
−
-type diffusion region
107
, the gate insulator film
108
and the gate electrode
120
form the p-channel MOS transistor
104
. The p-type collector diffusion region
109
is formed to be in contact with the p
−
-type diffusion region
107
. The first multi-field plates
112
a
to
112
c
consisting of conductor films of doped polysilicon or the like are formed on the major surface of the SOI layer
103
and the field oxide film
111
a
. An interlayer insulator film
113
is formed on the first multi-field plates
112
a
to
112
c
and the gate electrode
120
. The second multi-field plates
114
a
to
114
d
are formed on the interlayer insulator film
113
by aluminum wires or the like. The emitter electrode
116
is formed to be electrically connected with the p
+
-type emitter diffusion region
105
and the n-type emitter diffusion region
106
. The collector electrode
117
is formed to be electrically connected with the p-type collector diffusion region
109
and the n
+
-type collector diffusion region
110
. A glass-coated insulator film
115
is formed on the emitter electrode
116
, the collector electrode
117
and the second multi-field plates
114
a
to
114
d
. A trench isolation structure
118
including a field oxide film
111
b
is formed to be adjacent to the p-type collector diffusion region
109
. A back electrode
121
is formed along the overall back surface of the semiconductor substrate
101
.
The LIGBT having the sectional structure shown in
FIG. 51
is formed symmetrically about a centerline
119
, and has a substantially circular layout as shown in
FIG. 52
, for example.
FIG. 52
is a partially fragmented perspective view of an exemplary conventional LIGBT. While the LIGBT shown in
FIG. 52
has a circular layout, the layout of such an LIGBT is not restricted to the circular one but may be a square or rectangular one symmetrical about the centerline
119
.
An OFF operation of the conventional LIGBT shown in
FIG. 51
is now described with reference to FIG.
53
.
FIG. 53
is a typical sectional view for illustrating the OFF operation of the conventional LIGBT.
Referring to
FIG. 53
, the emitter electrode
116
is connected to a power source having a positive potential (+V) in the OFF operation of the conventional LIGBT. The gate electrode
120
is set at the same level as a power supply potential. The collector electrode
117
and the back electrode
121
are grounded and maintain a ground potential.
In this potential state, a depletion layer extends from a p-n junction part of a boundary surface J
1
between the p
−
-type diffusion region
107
and the p-type collector diffusion region
109
and the n
−
-type SOI layer
103
toward the n
−
-type SOI layer
103
. A first potential
122
is formed in the extending depletion layer. This is called a RESURF (reduced surface) effect, which is a basic technique employed for improving breakdown voltage of a lateral device.
In the conventional LIGBT, sharing of voltage load between the silicon and oxide films in the vertical direction is decided in response to the ratio between the dielectric constants thereof. In the transverse direction, on the other hand, the first and second multi-field plates
112
a
to
112
c
and
114
a
to
114
d
attain electric field relaxation. In other words, the first and second multi-field plates
112
a
to
112
c
and
114
a
to
114
d
homogenize the profile of the first potential
122
in the device surface area by capacitive coupling formed by the insulator and conductor films (this function is hereinafter referred to capacitive potential division). Consequently, it is possible to suppress occurrence of an avalanche phenomenon caused by electric field concentration resulting from local heterogeneity of the first potential
122
.
Thus, no voltage load is applied to the trench isolation structure
118
in the OFF operation of the conventional LIGBT. As shown in
FIG. 54
, the main function of the trench isolation structure
118
is to bear a second potential
125
generated when an external potential (V
EX
) is supplied to an external region
123
for maintaining isolation between the device and the external region
123
.
FIG. 54
is a typical sectional view for illustrating the function of the trench isolation structure
118
.
When the aforementioned LIGBT is applied to a high-side driver for a one-chip invertor, for example, the current drivability of the LIGBT must be improved, i.e., the amount of a feedable current must be increased. As a method for improving the current dlivability, it is effective to increase the channel width (peripheral length) of the gate electrode
120
(see FIG.
51
). In order to increase the peripheral length of the gate electrode
120
, the emitter electrode
116
and the collector electrode
117
of the LIGBT may be reversely arranged as shown in FIG.
55
.
FIG. 55
is a sectional view showing an LIGBT having reversely arranged emitter and collector electrodes
116
and
117
. Referring to
FIG. 55
, a gate electrode
120
is formed on a position separated from a centerline
119
as compared with that shown in
FIG. 51
, due to the reverse arrangement of the emitter electrode
116
and the collector electrode
117
. When the LIGBT is formed in a circular layout symmetrical about the centerline
119
, therefore, the peripheral length of the gate electrode
120
can be increased as compared with that shown in FIG.
51
. When the LIGBT is turned on, therefore, a larger amount of Hall current can be fed from the emitter electrode
116
to the collector electrode
117
through a p-channel MOS transistor
104
.
When the emitter electrode
116
and the collector electrode
117
are reversely arranged as shown in
FIG. 55
, however, breakdown
Jackson, Jr. Jerome
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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