Isolation structure and fabricating method therefor

Details Isolation structure and fabricating method therefor Isolation structure and fabricating method therefor

2000-03-17

2002-11-12

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Including isolation structure

C438S294000

Reexamination Certificate

active

06479361

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor isolation structure and fabricating method therefor. Particularly, the present invention relates to a semiconductor isolation structure and a fabricating method in which the size of the active region is kept from decreasing because of an increase in the size of the isolating region, by utilizing a trench.
2. Description of Related Art
As the density of semiconductor devices increases, reducing the size of an isolating region in such semiconductor devices is more and more important.
Generally, a semiconductor device is isolated by applying the LOCOS (local oxidation of silicon) method. In the LOCOS method, a pad oxide layer is formed between a silicon nitride layer and a semiconductor substrate by thermal oxidation in order to relieve stress caused by different rates of thermal expansion between the semiconductor device and the silicon nitride layer. The silicon nitride layer is formed on the active region and is used as a hard mask. Further, a field insulating layer defines a device isolating region which is formed by oxidizing the field region of the semiconductor substrate not covered by the silicon nitride layer. The field insulating layer grows in the vertical direction and in the horizontal direction relative to the substrate because of an oxidant (O
2
) diffusing along the pad oxide layer. Therefore, the field insulating layer grows under the pattern edge of the silicon nitride layer as well as on the field region.
The encroachment of the field insulating region into the active region is called a “bird's beak”. The length of the bird's beak eventually becomes one half of the thickness of the field insulating region. Therefore, if the size of the active region is to be kept from decreasing, the bird's beak must be minimized.
In order to reduce the length of the bird's beak, a conventional method is known in which the thickness of the field insulating region is decreased. However, if the thickness of the field insulating region is reduced in a 16M DRAM or higher, then parasitic capacitance between the wiring layer and the semiconductor substrate increases. Therefore, the signal transmitting speed is lowered. Further, parasitic transistors are formed in the isolating regions due to the wiring of the gate. Accordingly, the threshold voltage V
t
is lowered, with the result that the device isolating characteristics deteriorate.
Therefore, conventional methods are known in which the length of the bird's beak is decreased, and at the same time, the device isolating characteristics are improved. One of these methods is PBLOCOS (poly Si buffered LOCOS), in which the thickness of the stress absorbing pad oxide layer is reduced, and a poly crystalline silicon layer is inserted into between the semiconductor substrate and the silicon nitride layer. Another is SILO (sealed interface LOCOS) in which the side walls of the pad oxide layer are protected by a silicon nitride layer. A third one is recessed oxide LOCOS in which a recessed field insulating layer is formed on the field region of the semiconductor substrate.
However, in the above conventional methods, too precise a flatness and too precise a design rule are required to make these methods applicable to the 256M DRAM scale.
Therefore, in order to overcome the above problems, a BOX (buried oxide) type shallow trench isolation method is best known. In this method, a shallow trench is formed on the semiconductor substrate. Thereafter, a buried silicon oxide layer is deposited by a chemical vapor deposition method (CVD method). Therefore, the bird's beak is not formed, so the active region is not encroached. Further, the silicon oxide layer is buried into the trench and subsequently etched back, thereby obtaining a flat surface.
FIG. 1
is a sectional view showing an isolation structure according to the conventional art.
In this isolation structure, a field insulating layer
23
is formed within a trench
17
defining the isolating region of the semiconductor substrate
11
. That is, CVD is used to deposit the field insulating layer
23
into the trench
17
. For this purpose, after depositing an insulating layer
23
composed of silicon oxide or the like using CVD, the insulating layer is etched back so that the insulating layer
23
remains only within the trench
17
.
That is, the trench
17
is filled with the field insulating layer
23
by applying a CVD process instead of an oxidation process. Therefore the formation of the bird's beak is prevented. Further, etching back is performed so as to make the silicon oxide insulating layer
23
remain within the trench. A flat surface is therefore obtained.
FIGS. 2
to
5
illustrate a method for fabricating the above-described conventional isolation structure.
Referring to
FIG. 2
, a pad oxide layer
13
is formed on semiconductor substrate
11
by a thermal oxidation process. A silicon nitride layer
15
is formed on the pad oxide layer
13
by CVD. A photolithography process is then carried out to form a photolithographic pattern, so that predetermined portions of the pad oxide layer
13
and the silicon nitride layer
15
are removed to thereby expose the substrate
11
. This defines a device isolating region I
1
and an active region A
1
. By using the silicon nitride layer
15
as a mask, reactive ion etching (to be called “RIE” below) is carried out to form the trench
17
.
Referring to
FIG. 3
, silicon oxide is deposited by CVD to fill the trench
17
, thereby forming an insulating layer
19
. Here, because of the height difference between the surface of the silicon nitride layer
15
and the bottom of the trench
17
, a step is formed on the surface of the insulating layer
19
.
A photoresist layer
21
is coated on the insulating layer
19
. The photoresist layer
21
is patterned to expose locations corresponding to the silicon nitride layer
15
and to remain over locations corresponding to the trench
17
on the insulating layer
19
. Then by using the patterned photoresist layer
21
as a mask, the exposed portions of the insulating layer
19
are etched. Here, the etched surface of the insulating layer
19
is roughly as high as the top of the trench
17
.
Then, as shown in
FIG. 4
, the patterned photoresist layer
21
is removed. Then the insulating layer
19
is partially removed to expose the silicon nitride layer
15
by, for example, chemical-mechanical polishing process (to be called “CMP process” below).
Then, as shown in
FIG. 5
, a wet etching process is carried out to etch the pad oxide layer
13
and the silicon nitride layer
15
so as to expose the substrate
11
. Under this condition, the upper portion of the insulating layer
19
is also removed so that it remains only within the trench
17
. Furthermore, its surface becomes even with the substrate
11
, thereby ensuring a flat surface. Thus the insulating layer
19
which remains within the trench
17
becomes a field insulating layer
23
.
In this related art, when the pad oxide layer
13
is etched, the upper portion of the filled insulating layer
19
is also etched, and thus a field insulating layer
23
is formed. Under this condition, however, the insulating layer
19
is isotropically etched. Therefore, the field oxide layer is formed to collapse the field insulating layer at the portion which contacts the side wall of the trench. Due to the collapsed portion of the field insulating layer, when a subthreshold voltage is supplied, a hump phenomenon occurs. As a result, current leakage increases, and the refresh characteristics deteriorate. Further, the electric field is concentrated at the top edges of the trench. Therefore, the threshold voltage of the subsequently formed gate insulating layer becomes weak.
SUMMARY OF THE INVENTION
The present invention is intended to overcome the above-described disadvantages of the related art.
It is an object of the present invention to provide an isolation structure that avoids increased leakage currents and deterioratio

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