Fishing – trapping – and vermin destroying
Patent
1995-06-26
1996-03-12
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 69, 437 72, 148DIG50, H01L 2176
Patent
active
054985668
ABSTRACT:
An isolation region structure of a semiconductor device and a method for fabricating the same using both a buried oxide isolation technique and a local oxidation of silicon technique, thereby capable of having an advantage of high integrity. In the isolation region structure, narrow trenches are filled only with a polysilicon film whereas wide trenches are filled with a field oxide film and a polysilicon film so as to isolate adjacent active regions from each other. The isolation region structure includes a plurality of trenches including narrow ones and wide ones formed in the silicon substrate, a thin oxide film formed on a bottom surface and opposite side surfaces of each of the narrow trenches and opposite side surfaces of each of the wide trenches, a thick field oxide film formed on a bottom surface of each of the wide trenches, a thin nitride film formed to cover the entire surface of a portion of the thin oxide film disposed in each of the narrow trenches, opposite side surfaces of a portion of the thin oxide film disposed in each of the wide trenches and opposite edges of a portion of the thick field oxide film disposed in each of the wide trenches, a polysilicon film filling the narrow trenches and the wide trenches, another thick field oxide film formed over the polysilicon film, and a thin pad oxide film formed over the active regions.
REFERENCES:
patent: 4238278 (1980-12-01), Antipov
patent: 4666556 (1987-05-01), Fulton et al.
patent: 4766090 (1988-08-01), Coquin et al.
patent: 4892614 (1990-01-01), Chapman et al.
patent: 4960727 (1990-10-01), Mattox et al.
patent: 4980747 (1990-12-01), Hutter et al.
patent: 4983226 (1991-01-01), Hunter et al.
patent: 5011788 (1991-04-01), Kawasi et al.
Wolf; "Silicon Processing For The VLSI Era", vol. 1, Process Technology, Lattice Press, 1986, pp. 177-178.
Dang Trung
Hearn Brian E.
LG Semicon Co. Ltd.
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