Isolation region in a group III-V semiconductor device and metho

Details Isolation region in a group III-V semiconductor device and metho Isolation region in a group III-V semiconductor device and metho

1993-10-08

1995-03-21

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

With specified dopant

257289, 257499, 257617, H01L 2702, H01L 2712

Patent

active

053999002

ABSTRACT:
A semiconductor device having in a body of a group III-V semiconductor material at least one isolation region which is stable at temperatures up to about 900.degree. C. The isolation region is formed of ions of a group III or V element which are implanted into the body and then thermally annealed at a temperature of between 650.degree. C. and 900.degree. C. This provides the regions with voids which remove free carriers and makes the region highly resistive.

REFERENCES:
patent: 4837178 (1989-06-01), Ohshima et al.
patent: 5043777 (1991-08-01), Srirnm
Ko et al, "Correlation of Void Formation With the Reduction of Carrier Activation and Anomalous Dopant Diffusion in Si-Implanted GaAs", Procedures of Material Research Symposium, vol. 163, pp. 983-986 (1990).
Lee et al, "Void formation, electrical activation, and layer intermixing in Si-implanted GaAs/AlGaAs superlattices", Applied Physics Letters, vol. 57(4), pp. 389-391, Jul. 23, 1990.

Affiliated with

Also associated with

Rating

Isolation region in a group III-V semiconductor device and metho does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Isolation region in a group III-V semiconductor device and metho, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Isolation region in a group III-V semiconductor device and metho will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1151113