Isolation process for high-voltage semiconductor devices

Details Isolation process for high-voltage semiconductor devices Isolation process for high-voltage semiconductor devices

1983-09-29

1986-02-25

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29580, 148175, 148DIG50, 148DIG85, 357 42, 357 49, H01L 2176

Patent

active

045718180

ABSTRACT:
A semiconductor structure including a pair of single-crystal semiconductor bulk regions (10.3, 12.2) of differing first and second bulk conductivities, respectively, for forming semiconductor circuits therein, is fabricated whereby each such region is electrically isolated from the other and from a rigid body (20) supporting these regions. The structure is formed by forming at a major surface of a single crystal semiconductor water (10) having the first bulk conductivity a bulk zone (12.1) having the second bulk conductivity, followed by the steps of (1) forming in the wafer (10) at the major surface (10.6) thereof a V-shaped groove (10.2) at the boundary of the bulk zone (12.1) using a crystallographic orientation dependent etch, in order to define the regions (10.3, 12.2) of differing conductivities, (2) forming a dielectric layer (15.1, 15.2) upon the walls of the V-groove and upon the exposed portion of the major surface, (3) forming a rigid body layer (20), such as polysilicon, upon the dielectric layer (15.1, 15.2), and (4) planarizing the exposed, opposed major surface of the single crystal medium down to the vertices of the V-grooves. The semiconductor circuits themselves can then be fabricated in the resulting mutually dielectrically isolated regions (10.3, 12.2).

REFERENCES:
patent: 3895392 (1975-07-01), Polata et al.
patent: 3953255 (1976-04-01), Combs, Jr.
patent: 4017341 (1977-04-01), Suzuki et al.
patent: 4056413 (1977-11-01), Yoshimura
patent: 4393573 (1983-07-01), Kato et al.
patent: 4408386 (1983-10-01), Takagashiki et al.
Beasom, J. D., "A Process for Simultaneous Fabrication of Vertical NPN and DNP's, Nch and Pch MOS Devices", in 1973 International Electron Devices Meeting Technical Digest, Dec. 1973, pp. 41-43.
"Dielectric Isolation: Comprehensive, Current and Future," K. E. Bean et al, Journal of the Electrochemical Society, vol. 124, No. 1, Jan. 1977, pp. 5C-12C.
"A New Complementary Dielectric Isolation Process for High-Voltage Devices," T. Sakurai et al, IEEE Transactions on Electron Devices, vol. ED-28, No. 10, Oct. 1981, pp. 1199-1201.

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