Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal
Reexamination Certificate
2005-05-24
2008-10-07
Dang, Phuc T (Department: 2892)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
C438S510000, C438S514000, C438S527000, C438S529000
Reexamination Certificate
active
07432121
ABSTRACT:
A barrier implanted region of a first conductivity type formed in lieu of an isolation region of a pixel sensor cell that provides physical and electrical isolation of photosensitive elements of adjacent pixel sensor cells of a CMOS imager. The barrier implanted region comprises a first region having a first width and a second region having a second width greater than the first width, the second region being located below the first region. The first region is laterally spaced from doped regions of a second conductivity type of adjacent photodiodes of pixel sensor cells of a CMOS imager.
REFERENCES:
patent: 6218691 (2001-04-01), Chung et al.
patent: 7102184 (2006-09-01), Rhodes
patent: 7262110 (2007-08-01), Jin
patent: 2002/0121655 (2002-09-01), Zheng et al.
patent: 2004/0094784 (2004-05-01), Rhodes et al.
patent: 2004/0235215 (2004-11-01), Komori
patent: 2005/0035382 (2005-02-01), Shinohara et al.
patent: 2006/0065896 (2006-03-01), Abe et al.
patent: WO 00/21280 (2000-04-01), None
Brady Frederick
Patrick Inna
Dang Phuc T
Dickstein & Shapiro LLP
Micro)n Technology, Inc.
Tran Thanh Y
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