Isolation methods in semiconductor devices

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257SE21001

Reexamination Certificate

active

11021032

ABSTRACT:
Methods of forming a device isolation layer in a semiconductor substrate are disclosed. A disclosed method includes: forming a trench in a field area of a semiconductor substrate, growing a SiON layer on an inside of the trench by annealing in an ambience of NO gas, and filling the trench with a trench-fill material.

REFERENCES:
patent: 6291300 (2001-09-01), Fukazawa et al.
patent: 6306741 (2001-10-01), Lee et al.
patent: 6333232 (2001-12-01), Kunikiyo
patent: 6383911 (2002-05-01), Mikagi
patent: 6661043 (2003-12-01), Huang et al.
patent: 6696360 (2004-02-01), Ahn et al.
patent: 6709951 (2004-03-01), Beyer et al.
patent: 2002/0086495 (2002-07-01), Yoo et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Isolation methods in semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Isolation methods in semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Isolation methods in semiconductor devices will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3779958

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.