Isolation method in a semiconductor device

Details Isolation method in a semiconductor device Isolation method in a semiconductor device

1997-01-10

1998-03-24

Dang, Trung

Fishing, trapping, and vermin destroying

437 69, 437 70, 437228TR, 437228ME, 148DIG50, H01L 2176

Patent

active

057312214

ABSTRACT:
The present invention discloses an isolation method in a semiconductor device. The method includes the steps of: forming a pad oxide film, a buffer polysilicon layer, and a nitride layer in that order on a semiconductor substrate where cell region and peripheral region having respective device isolation regions are defined; etching the nitride layer and the buffer polysilicon layer on the device isolation regions of the cell region and the peripheral region; forming a field oxide layer on the device isolation regions of the cell region and the peripheral region; etching the field oxide layer except for edge portions to expose the substrate in the device isolation regions of the cell region and the peripheral region; forming a first insulating layer on the substrate resulting from the previous etching step; etching the first insulating layer, to form a spacer in the side wall of the field oxide layer on the exposed substrate; etching the exposed substrate to form a trench; forming a second insulating layer on the substrate where the trench is formed, to fill the trench with the second insulating layer; etching the second insulating layer to planarize the surface of the substrate; and removing the nitride layer and the buffer polysilicon layer.

REFERENCES:
patent: 4745081 (1988-05-01), Beyer et al.
patent: 5362669 (1994-11-01), Boyd et al.
patent: 5468676 (1995-11-01), Madan
patent: 5470782 (1995-11-01), Schwalke et al.
patent: 5571738 (1996-11-01), Paterson et al.

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