Isolation layer of semiconductor device and method for fabricati

Details Isolation layer of semiconductor device and method for fabricati Isolation layer of semiconductor device and method for fabricati

1996-10-22

1998-06-30

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438413, 438424, 438481, H01L 2176

Patent

active

057733511

ABSTRACT:
An isolation layer structure of a semiconductor device includes a substrate; a first insulating layer having a predetermined width and thickness which is formed in a predetermined portion of the substrate; and a second insulating layer which is formed in a predetermined portion of the substrate and which surrounds the first insulating layer.

REFERENCES:
patent: 5254218 (1993-10-01), Roberts et al.
patent: 5472902 (1995-12-01), Lur
"Characteristics of CMOS Device Isolation for the ULSI Age", Bryant, Andres et al., IEDM 94, pp. 671-674, 1994.

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