Isolation for high density integrated circuits

Details Isolation for high density integrated circuits Isolation for high density integrated circuits

1981-08-27

1984-06-19

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29580, 29577R, 29578, 148 15, 148175, 148187, 156643, 156648, 357 50, 357 49, H01L 2176

Patent

active

044546475

ABSTRACT:
An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends through the recessed dielectric portion and extends further into the monocrystalline silicon body than the recessed portion. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

REFERENCES:
patent: 3534234 (1970-10-01), Clevenger
patent: 3648125 (1972-03-01), Peltzer
patent: 3753803 (1973-08-01), Nomura et al.
patent: 3886587 (1975-05-01), Nicolay
patent: 3900350 (1975-08-01), Appels et al.
patent: 3958040 (1976-05-01), Webb
patent: 3961999 (1976-06-01), Antipov
patent: 3966514 (1976-06-01), Feng et al.
patent: 3966577 (1976-06-01), Hochberg
patent: 3970486 (1976-07-01), Kooi
patent: 3997378 (1976-12-01), Kaji et al.
patent: 4002511 (1977-01-01), Magdo et al.
patent: 4056415 (1977-11-01), Cook et al.
patent: 4104086 (1978-08-01), Bondur et al.
patent: 4135954 (1979-01-01), Chang et al.
patent: 4140558 (1979-02-01), Murphy et al.
patent: 4170492 (1979-10-01), Bartlett
patent: 4256514 (1981-03-01), Pogge
patent: 4325182 (1982-04-01), Tefft et al.
patent: 4369565 (1983-01-01), Muramatsu
IBM Technical Disclosure Bulletin, vol. 20, No. 1, Jun. 1977, "Recessed Oxide Isolation Process" by S. A. Abbas.

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