Isolation circuit for I/O terminal

Details Isolation circuit for I/O terminal Isolation circuit for I/O terminal

1997-10-09

1999-06-22

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Parallel controlled paths

327389, 327401, H03K 1762

Patent

active

059146273

ABSTRACT:
Circuits and method for isolating internal nodes of an integrated circuit from external signals applied to I/O terminals of the IC even under no-power conditions are disclosed. The invention senses the most positive voltage level (in case of a p-channel implementation) or the most negative voltage level (in case of an n-channel implementation) at two input or input/output (I/O) pads and uses that voltage to isolate the internal nodes of the integrated circuit from the pad, without requiring the circuit power supply for its operation.

REFERENCES:
patent: 4397000 (1983-08-01), Nagami
patent: 4403192 (1983-09-01), Williman
patent: 4634895 (1987-01-01), Luong
patent: 4841180 (1989-06-01), Kraus
patent: 5022007 (1991-06-01), Arimoto et al.
patent: 5623446 (1997-04-01), Hisada et al.
patent: 5625308 (1997-04-01), Matsumoto et al.
patent: 5828241 (1998-10-01), Sukegawa

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