Isolation by active transistors with grounded gates

Details Isolation by active transistors with grounded gates Isolation by active transistors with grounded gates

1996-08-28

1998-10-13

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257499, 257368, H01L 2900, H01L 2976

Patent

active

058216006

ABSTRACT:
An isolation gate structure is formed between active areas on a P-type semiconductor substrate. The isolation structure includes a thick gate oxide layer over which is formed a P-doped polycrystalline silicon layer. The polycrystalline silicon layer is electrically connected to the substrate, by buried contact if desired, and can further be electrically connected to a source region formed within the active area. The polycrystalline silicon layer and substrate are connected to ground potential, thus preventing current flow between active areas.

REFERENCES:
patent: 4141027 (1979-02-01), Baldwin et al.
patent: 4262298 (1981-04-01), Tuan et al.
patent: 4513304 (1985-04-01), Takemae
patent: 4561170 (1985-12-01), Doering et al.
patent: 4570331 (1986-02-01), Eaton, Jr. et al.
patent: 4853894 (1989-08-01), Yamanaka et al.
patent: 4900693 (1990-02-01), Manning
patent: 4960725 (1990-10-01), Noguchi
patent: 4994893 (1991-02-01), Ozaki et al.
patent: 4996575 (1991-02-01), Ipri et al.
patent: 4998161 (1991-03-01), Kimura et al.
patent: 5043790 (1991-08-01), Butler
patent: 5067000 (1991-11-01), Eimori et al.
patent: 5104822 (1992-04-01), Butler
patent: 5151759 (1992-09-01), Vinal
patent: 5162890 (1992-11-01), Butler
patent: 5164803 (1992-11-01), Ozaki et al.
patent: 5164806 (1992-11-01), Nagatomo et al.
patent: 5221419 (1993-06-01), Beckett
patent: 5225704 (1993-07-01), Wakamiya et al.
patent: 5320975 (1994-06-01), Cederbaum et al.
patent: 5550397 (1996-08-01), Lifshitz et al.
patent: 5633524 (1997-05-01), Ueda et al.
"Selective removal of polysilicon to obtain improved masterslice," IBM Technical Disclosure Bulletin 31(4); 249-252, 1988.
Abbas, S.A., et al., "Low-leakage, N-channel silicon gate FET with a self-aligned field shield," IEDM Technical Digest, IBM System Products Div., N.Y., 1973, pp. 371-373.
Terman, L.M., "Aluminum-silicon self-aligned gate process with field shield," IBM Technical Disclosure Bulletin 15(9): 2852-2854, Feb. 1973.
Krick, P.J., "Triple density MNOS memory array with field shield," IBM Technical Disclosure Bulletin 16(6): 1723-1725, Nov. 1973.
Kalter, H.L.; Vanderslice, W.B., Jr., "Making a one-device memory cell," IBM Technical Disclosure Bulletin 18(4): 1019-1020, Sep. 1975.
Koyanagi, M.; Sunami, H.; Hashimoto, N.; Ashikawa, M. "Novel high density, stacked capacitor MOS RAM," IEDM Technical Digest, IBM System Products Div., N.Y., 1978, pp. 348-351.
Erb, D.M.; McCombs, A.; Radwin, M. "Hi-C isolation of DRAM storage capacitors," IEDM Technical Digest, IBM System Products Div., N.Y., 1982, pp. 612-615.
Shimizu, M.; Inuishi, M.; Ogawa, T.; Miyatake, H.; Tsukamoto, K.; Akasaka, Y. "Deep submicron device isolation with buried insulator between source/drain polysilicon . . . ," IEDM Technical Digest, IBM System Products Div., N.Y., 1988, pp. 96-99.
Wakamiya, W.; Timori, T.; Ozaki, H.; Itoh, H.; Fujiwara, K.; Shibano, T.; et al. "Fully planarized 0.5 .mu.m technologies for 16M DRAM," IEDM Technical Digest, IBM System Products Div., N.Y., 1988, pp. 246-249.
Manchanda, L.; Hellenius, S.J.; Lynch, W.T.; Cong, H.-i.; Ng, K.K.; et al. "A high-performance directly insertable self-aligned ultra-rad-hard and enhanced isolation field-oxide technology . . . ," IEEE Transactions on Electron Devices 36(4): 651-658, 1989.
Iwamatsu, T.; Yamaguchi, Y,; Inoue, Y.; Nishimura, T.; Tsubouchi, N. "CAD-compatible high-speed CMOS/SIMOX technology using field-shield isolation . . . ," IEDM Technical Digest, IBM System Products Div., N.Y., 1993, pp. 475-478, 1993.

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