Isolated well and method of making

Details Isolated well and method of making Isolated well and method of making

1993-09-13

1995-02-28

Carroll, J.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

With pn junction isolation

257548, 257549, 437 77, H01L 2702, H01L 2704, H01L 272

Patent

active

053940075

ABSTRACT:
A junction isolated P-well is formed for high performance BiCMOS. Two dopants of opposite conductivity types are implanted and co-diffused inside an annular N-type region to form a narrow N-type buried layer positioned between two P-type regions. N-type buried layer is formed having P-type doped regions above and below the N-type buried layer so that the N-type buried layer is narrow. The P-type region above the N-type buried layer provides for a retrograde profile of the P-well formed above it. Besides the P-well isolation, the P-type region below the N-type buried layer acts as a ground plane which collects noise, which helps to prevent it from being coupled to other devices of the BiCMOS circuit.

REFERENCES:
patent: 3502951 (1970-03-01), Hunts
patent: 5162252 (1992-11-01), Kanda et al.

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