Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Mesa structure
Reexamination Certificate
2011-07-05
2011-07-05
Mandala, Victor (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
Mesa structure
C257S213000, C257S401000, C257S288000, C257SE29112, C257SE29005, C257SE21014
Reexamination Certificate
active
07973389
ABSTRACT:
A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.
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International Search Report and Written Opinion received for PCT Patent Application No. PCT/US2008/068855, mailed on Dec. 30, 2008, 10 pages.
International Preliminary Report on Patentability received for PCT Patent Application No. PCT/US2008/068855, mailed on Jan. 28, 2010, 6 pages.
Cea Stephen M.
Kavalieros Jack
Rios Rafael
Engineer Rahul D.
Intel Corporation
Mandala Victor
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