Isolated trench MOSFET in epi-less semiconductor sustrate

Details Isolated trench MOSFET in epi-less semiconductor sustrate Isolated trench MOSFET in epi-less semiconductor sustrate

2007-12-17

2010-06-15

Richards, N Drew (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S350000, C257S351000, C257S500000, C257S501000, C257S510000, C257S524000, C257SE29258, C438S353000, C438S359000

Reexamination Certificate

active

07737526

ABSTRACT:
An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. A MOSFET is formed in the isolated pocket.

REFERENCES:
patent: 4269636 (1981-05-01), Rivoli et al.
patent: 4454647 (1984-06-01), Joy et al.
patent: 4478655 (1984-10-01), Nagakubo et al.
patent: 4642883 (1987-02-01), Sakurai et al.
patent: 4655875 (1987-04-01), Wada et al.
patent: 4819052 (1989-04-01), Hutter
patent: 4980747 (1990-12-01), Hutter et al.
patent: 5374569 (1994-12-01), Yilmaz et al.
patent: 5386136 (1995-01-01), Williams et al.
patent: 5410175 (1995-04-01), Kyomasu et al.
patent: 5420061 (1995-05-01), Manning
patent: 5485027 (1996-01-01), Williams et al.
patent: 5506431 (1996-04-01), Thomas
patent: 5525824 (1996-06-01), Himi et al.
patent: 5557135 (1996-09-01), Hashimoto
patent: 5668397 (1997-09-01), Davis et al.
patent: 5684305 (1997-11-01), Pearce
patent: 5807783 (1998-09-01), Gaul et al.
patent: 5883413 (1999-03-01), Ludikhuize
patent: 5892264 (1999-04-01), Davis et al.
patent: 5986863 (1999-11-01), Oh
patent: 6013936 (2000-01-01), Colt
patent: 6130458 (2000-10-01), Takagi et al.
patent: 6144086 (2000-11-01), Brown et al.
patent: 6163052 (2000-12-01), Liu et al.
patent: 6331456 (2001-12-01), Wu
patent: 6383892 (2002-05-01), Colt
patent: 6559505 (2003-05-01), Fallica
patent: 6657262 (2003-12-01), Patti
patent: 6740958 (2004-05-01), Nakazato et al.
patent: 6855985 (2005-02-01), Williams et al.
patent: 6900091 (2005-05-01), Williams et al.
patent: 6943426 (2005-09-01), Williams et al.
patent: 7009271 (2006-03-01), Thurgate et al.
patent: 7049663 (2006-05-01), Wang
patent: 7176548 (2007-02-01), Williams et al.
patent: 7183610 (2007-02-01), Pattanayak et al.
patent: 7268045 (2007-09-01), Hower et al.
patent: 2001/0000288 (2001-04-01), Oh
patent: 2001/0013636 (2001-08-01), Dunn et al.
patent: 2001/0015459 (2001-08-01), Watanabe et al.
patent: 2002/0008299 (2002-01-01), Leonardi
patent: 2002/0084506 (2002-07-01), Voldman et al.
patent: 2003/0107103 (2003-06-01), Iwata et al.
patent: 2003/0168712 (2003-09-01), Shin et al.
patent: 2004/0026746 (2004-02-01), Nakazawa et al.
patent: 2004/0032005 (2004-02-01), Williams et al.
patent: 2004/0033666 (2004-02-01), Williams et al.
patent: 2005/0014324 (2005-01-01), Williams et al.
patent: 2005/0014329 (2005-01-01), Williams et al.
patent: 2005/0142724 (2005-06-01), Williams et al.
patent: 2005/0142791 (2005-06-01), Williams et al.
patent: 2005/0142792 (2005-06-01), Williams et al.
patent: 2005/0158939 (2005-07-01), Williams et al.
patent: 2005/0179093 (2005-08-01), Morris
patent: 2005/0179111 (2005-08-01), Chao
patent: 2005/0189606 (2005-09-01), Nakagawa
patent: 2005/0272207 (2005-12-01), Williams et al.
patent: 2005/0272230 (2005-12-01), Williams et al.
patent: 2005/0287765 (2005-12-01), Onai et al.
patent: 2006/0076629 (2006-04-01), Yilmaz
patent: 2006/0175635 (2006-08-01), Arai et al.
patent: 2006/0223257 (2006-10-01), Williams et al.
patent: 2007/0013021 (2007-01-01), Zhang
patent: 2007/0132056 (2007-06-01), Williams et al.
patent: 2007/0158779 (2007-07-01), Cannon et al.
patent: 2007/0241421 (2007-10-01), Liu et al.
patent: 2007/0278568 (2007-12-01), Williams et al.
patent: 2007/0278612 (2007-12-01), Williams et al.
patent: 2008/0042232 (2008-02-01), Williams et al.
patent: 2008/0044978 (2008-02-01), Williams et al.
patent: 2008/0048287 (2008-02-01), Williams et al.
patent: 2008/0191277 (2008-08-01), Disney et al.
patent: 2008/0197408 (2008-08-01), Disney et al.
patent: 2008/0197445 (2008-08-01), Disney et al.
patent: 2008/0197446 (2008-08-01), Disney et al.
patent: 2008/0210980 (2008-09-01), Disney et al.
patent: 2008/0213972 (2008-09-01), Disney et al.
patent: 2008/0217699 (2008-09-01), Disney et al.
patent: 2008/0230812 (2008-09-01), Disney et al.
patent: 2008/0237656 (2008-10-01), Williams et al.
patent: 2008/0237704 (2008-10-01), Williams et al.
patent: 2008/0237706 (2008-10-01), Williams et al.
patent: 2008/0237782 (2008-10-01), Williams et al.
patent: 2008/0237783 (2008-10-01), Williams et al.
patent: 2008/0290449 (2008-11-01), Williams et al.
patent: 2008/0290450 (2008-11-01), Williams et al.
patent: 2008/0290451 (2008-11-01), Williams et al.
patent: 2009/0020811 (2009-01-01), Voldman
patent: 2009/0101937 (2009-04-01), Lee et al.
patent: 2009/0236683 (2009-09-01), Williams et al.
patent: 0 589 675 (1994-03-01), None
patent: 1357598 (2003-10-01), None
patent: 2 362 508 (2001-11-01), None
patent: 10-0456691 (2008-11-01), None

Affiliated with

Also associated with

Rating

Isolated trench MOSFET in epi-less semiconductor sustrate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Isolated trench MOSFET in epi-less semiconductor sustrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Isolated trench MOSFET in epi-less semiconductor sustrate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4222685