Isolated scan paths

Details Isolated scan paths Isolated scan paths

1997-03-28

1999-03-23

Nguyen, Hoa T.

Excavating

371 2232, 371 2234, G01R 3128

Patent

active

058870040

ABSTRACT:
A method of isolating scan paths in an integrated circuit to reduce the RC delay associated with the scan paths and reduce power consumption, and to further enhance the capacitive decoupling of the power supply to reduce noise. The scan path can be connected to a data-storage element (latch or flip-flop) by a CMOS transmission gate, a single PMOS or NMOS transistor, or a logic gate (such as a NAND gate). The data-storage element is tested using either a scan-enable line, or the scan clock which is also connected to the data-storage element as an input. When the scan-enable line (or scan clock) is turned on, the scan path is connected to the output of the data-storage element.

REFERENCES:
patent: 4495629 (1985-01-01), Zasio et al.
patent: 4698588 (1987-10-01), Hwang et al.
patent: 4731553 (1988-03-01), Van Lehn et al.
patent: 4782283 (1988-11-01), Zasio
patent: 4812678 (1989-03-01), Abe
patent: 4855623 (1989-08-01), Flaherty
patent: 5032783 (1991-07-01), Hwang et al.
patent: 5107148 (1992-04-01), Millman
patent: 5237213 (1993-08-01), Tanoi
patent: 5392297 (1995-02-01), Bell et al.
patent: 5444288 (1995-08-01), Jacobs

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