Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation
Patent
1992-07-14
1994-02-15
Mintel, William
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With pn junction isolation
257343, 257409, 257492, 257547, H01L 2900, H01L 2976, H01L 2994, H01L 2358
Patent
active
052869954
ABSTRACT:
A power transistor having an epitaxial layer within an isolation region is formed in a semiconductor substrate. A buried diffusion within the substrate with vertical diffusions contacting it form the isolation region. A drain, source, gate, and drift region are formed within the epitaxial layer such that a RESURF LDMOS transistor is formed having its source isolated from the substrate. Multiple power transistors may share the buried isolation region. A P type semiconductor substrate allows the power transistor and high performance CMOS circuitry to be formed on the same semiconductor die.
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patent: 4890146 (1989-12-01), Williams et al.
patent: 4969030 (1990-11-01), Musumeci et al.
patent: 4994904 (1991-02-01), Nakagawa et al.
patent: 5072267 (1991-12-01), Hattori
patent: 5087954 (1992-02-01), Shirai
patent: 5156989 (1992-10-01), Williams et al.
IEDM Technical Digest, Dec. 3-5, 1979, "High voltage thin layer devices (RESURE DEVICES)", by Appels et al., pp. 238-241.
Donaldson Richard
Eschweiler Thomas G.
Grossman Rene E.
Loke Steven
Mintel William
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