Isolated P-well architecture for a memory device

Details Isolated P-well architecture for a memory device Isolated P-well architecture for a memory device

2011-04-05

2011-04-05

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Floating gate

Disturbance control

C365S186000, C365S185210, C365S185180, C365S185330

Reexamination Certificate

active

07920419

ABSTRACT:
A memory device and a method to prevent or reduce program disturb by isolating P-wells of strings in a non-volatile memory array. During a program operation, the isolated P-wells may be coupled to corresponding bitlines, which may be selected or inhibited, and may be at different voltages. During erase, read, and verify operations, the isolated P-wells may be coupled to source.

REFERENCES:
patent: 5734609 (1998-03-01), Choi et al.
patent: 7157771 (2007-01-01), Forbes
patent: 7570517 (2009-08-01), Kwak et al.

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