Isochronous synchronizer

Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data

Reexamination Certificate

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Reexamination Certificate

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07839963

ABSTRACT:
Circuitry for synchronizing communications between clock environments wherein a change of state is transmitted from a first clock environment to a second clock environment, the first clock environment being timed by a first clock signal and the second clock environment being timed by a second clock signal, the first and second clock signals having nominally the same frequency but an unknown phase relationship, the circuitry comprising: delay means in the first clock environment arranged to generate a plurality of timing signals by delaying said first clock signal by respectively different delay values; sampling means in the second clock environment for sampling said plurality of timing signals at timing determined by said second clock signal thereby generating a plurality of sampled timing signals; and determining means for generating a control signal based on said plurality of sampled timing signals and outputting said control signal for controlling the transfer time of said change of state.

REFERENCES:
patent: 5099477 (1992-03-01), Taniguchi et al.
patent: 2004/0051569 (2004-03-01), Jeon
patent: 2004/0066870 (2004-04-01), Gabara et al.
patent: 2005/0008111 (2005-01-01), Suzuki
patent: 2005/0229127 (2005-10-01), Warren
patent: 0 511 836 (1992-11-01), None
Communication pursuant to Article 94(3) EPC dated Aug. 25, 2008 in European Patent Application No. 05 257 786.3.

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