Multiplex communications – Wide area network – Packet switching
Patent
1992-11-02
1995-04-11
Hsu, Alpus
Multiplex communications
Wide area network
Packet switching
3701053, 370108, H04J 306, H04L 700
Patent
active
054065593
ABSTRACT:
A data transfer delay compensation system for a data communications system having a first transceiver and a second transceiver wherein the first transceiver includes circuitry for transferring an external cycle reference signal and a cycle delay signal to the second transceiver. The second transceiver includes circuitry for transmitting the received cycle reference back to the first transceiver a given time period after receipt of the cycle reference. The first transceiver receives the cycle reference transmitted from the second transceiver and measures a phase difference between the received cycle reference and the external cycle reference signal in order to update the cycle delay signal.
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Edem Brian C.
Evans Michael S.
Worsley Debra J.
Hsu Alpus
National Semiconductor Corporation
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