Irregular pitch layout for a semiconductor memory device

Details Irregular pitch layout for a semiconductor memory device Irregular pitch layout for a semiconductor memory device

1995-03-13

1997-06-03

Nelms, David C.

Static information storage and retrieval

Interconnection arrangements

365 51, 365205, G11C 506

Patent

active

056361580

ABSTRACT:
A layout arrangement for a semiconductor memory device provides additional space for locating an additional circuit device in a pitch limited circuit. A space or vacated area is created by laying out a circuit element in a manner in which the pitch of the circuit element and an adjacent circuit element is less than the pitch of two times the pitch of a connecting wire pair in a double-sided layout or less than the pitch of one connecting wire pair.

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