Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated
Reexamination Certificate
2000-12-30
2002-06-18
Ho, Hoai V. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
C257S778000
Reexamination Certificate
active
06407462
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit packaging, and more particularly to a an integrated circuit die solder bump arrangement useful in connection with flip-chip packages. The invention also relates to a routing scheme for a substrate upon which such a die may be mounted.
2. Description of the Related Art
Flip-chips are becoming an increasingly popular package for integrated circuits.
FIG. 1
illustrates a conventional flip-chip type package. As shown, a semiconductor die
10
has a series of gates or other logic elements constructed on its downward-facing (active) surface
11
, which has a plurality of solder bumps
19
disposed thereon in the form of a regularly spaced grid (i.e. all solder bumps line up across rows and columns). The die
10
is mounted to a substrate
13
which is then affixed to a printed circuit board (PCB)
14
. Die
10
is bonded to the substrate
13
by the solder bumps
19
on the surface
11
. In turn, the substrate
13
has a bottom surface
15
that comprises a plurality of solder balls
18
that electrically couple with bond pads on a top surface
17
of the PCB
14
.
FIG. 2
shows a cross section of the substrate
13
. As shown, a top surface
20
traces
22
for routing outer rows of the solder bumps
19
. Each of the traces
22
connects to a corresponding one of a plurality of vias
35
, which are in turn connected to solder balls (not shown). A plurality of vias
23
connects respective ones of the inner rows of the plurality of solder bumps
19
with traces
24
on a surface
26
, along which they are routed. The traces
24
are routed along the surface
26
and connect to a plurality of vias
34
, which connect the traces
24
to the traces
22
on the surface
20
. The traces
22
, in turn, connects to a plurality of vias
35
that extend through the substrate
13
and couple to corresponding one of the solder balls
18
. Power and ground solder bumps are connected by respective pluralities of vias
28
and
30
to power and ground planes
32
and
29
, respectively. (For purposes of clarity,
FIG. 2
omits many well known details regarding connections between traces, vias, planes, etc.).
High performance ICs frequently require hundreds or even thousands of interconnections for input/output (I/O) or power and ground. Flip-chip interconnections must satisfy power ratio constraints, where the number of I/O interconnections drive the total number of power connections on the chip. The ratio between the number of I/O connections and power connections to support modern chip specifications are in the 4 to 1 range. I/O to power ratios of 5 to 1 or 6 to 1 are not unusual. If the ratio is 6 to 1, there can be no more than six times as many I/O connections as power source connections can exist between the die and the package. For every power source connection there is one ground source connection (i.e. the signal/power/ground ratio is 6:1:1).
The large number of connections in combination with the constraint regarding the ratio between signal, power and ground signals poses difficult problems for the design of a solder bump layout on the surface
11
. It would be desirable to improve upon the routing density afforded by conventional solder bump pad arrangements according to which solder bump pads are laid out in a regular grid.
SUMMARY OF THE INVENTION
The present invention is an efficient layout for solder bump pads on an integrated die. The present invention also comprises a corresponding substrate for mounting such an integrated circuit die. According to the present invention, a first plurality of solder bumps are arranged the active surface of an integrated circuit die in the form of a grid comprising a plurality of rows and a plurality of columns, where the plurality of rows are parallel to two opposing edges of the active surface and the plurality of columns are perpendicular to the plurality of rows. The plurality of columns are separated by a distance D. Each of the solder bumps in every other row is separated from an adjacent solder bump in that row by a distance 2D such that the each of these solder bumps is disposed along a first group of the plurality of columns. Each of the solder bumps in the remaining rows, is separated from an adjacent solder bump in that row by the distance 2D such that the solder bumps in the remaining rows are disposed along a second group of the plurality of columns. Each column within the second group of columns is adjacent to, and in between, two of the columns within the first group of columns. In other words, the solder bump pads are staggered.
A substrate corresponding to the above described die is also disclosed. On the top surface of the substrate, via pads are interleaved with solder bump pads along rows which correspond to the inner rows (i.e. the rows closest to the center of the die) of the die grid. Each of the via pads is connected by a short trace to a corresponding solder bump pad in an adjacent row in the same column. Outer rows of solder bump pads are routed by traces along the top surface of the substrate. The inner rows are routed through vias that connect to the via pads; solder bump pads corresponding to signal I/O are routed along another substrate layer while solder bump pads corresponding to reference I/O (e.g. I/O power or ground) are routed through vias that connect to the via pads to reference planes.
Staggering the solder bumps enables traces on the substrate to be routed between solder bump pads that are in adjacent rows and adjacent columns or between via pads that are in adjacent rows and adjacent columns. In this manner, the present invention provides for a highly space efficient routing arrangement.
REFERENCES:
patent: 5376588 (1994-12-01), Pendse
patent: 5696027 (1997-12-01), Crane, Jr. et al.
patent: 5952726 (1999-09-01), Liang
patent: 6048753 (2000-04-01), Farnworth et al.
patent: 6064113 (2000-05-01), Kirkman
patent: 6111756 (2000-08-01), Moresco
patent: 6198635 (2001-03-01), Shenoy et al.
Banouvong Nikon
Ghahghahi Farshad
Ho Hoai V.
LSI Logic Corporation
Nguyen Thinh
Westman Champlin & Kelly
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