IP cores in reconfigurable three dimensional integrated...

Details IP cores in reconfigurable three dimensional integrated... IP cores in reconfigurable three dimensional integrated...

2008-09-12

2011-10-25

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S121000, C716S128000, C716S138000, C708S001000, C708S130000, C708S139000, C708S230000, C326S038000, C326S041000, C326S047000, C326S101000

Reexamination Certificate

active

08046727

ABSTRACT:
The invention describes IP cores applied to 3D FPGAs, CPLDs and reprogrammable SoCs. IP cores are (a) used for continuously evolvable hardware using 3D logic circuits, (b) applied with optimization metaheuristic algorithms, (c) applied by matching combinatorial logic of netlists generated by Boolean algebra to combinatorial geometry of CPLD architecture by reaggregating IP core elements and (d) used to effect continuous recalibration of IP cores with evolvable hardware in indeterministic environments for co-evolutionary reprogrammability.

REFERENCES:
patent: 7307449 (2007-12-01), Redgrave et al.
patent: 7822881 (2010-10-01), Vorbach et al.
patent: 7839166 (2010-11-01), Schmit et al.
Meleis et al., “Architectural Design of a Three Dimensional FPGA”, Proceedings of the Seventeenth Conference on Advanced Research in VLSI, Sep. 15-16, 1997, pp. 256-268.
Chiricescu et al., “A Three-Dimensional FPGA with an Integrated Memory for In-Application Reconfiguration Data”, Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, vol. 2, May 31-Jun. 3, 1998, pp. 232-235.
Rahman et al., “Wiring Requirement and Three-Dimensional Integration Technology for Field Programmable Gate Arrays,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, No. 1, Feb. 2003, pp. 44-54.

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