Ionizing dose hardness assurance technique for CMOS...

Details Ionizing dose hardness assurance technique for CMOS... Ionizing dose hardness assurance technique for CMOS...

2000-01-18

2002-11-05

Sherry, Michael J. (Department: 2829)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

C324S765010

Reexamination Certificate

active

06476597

ABSTRACT:

1.0 FIELD OF INVENTION
The present invention relates to testing procedures that can be used to determine the sensitivity of integrated circuits to ionizing doses of radiation in advance of their actual exposure to radiation of the type and intensity to which they will be exposed in their intended application. More particularly, it relates to a scheme for pre-irradiating silicon integrated circuits at low levels and determining their sensitivity to future radiation exposure at much higher levels. Furthermore, the adverse effects of the low level exposure can then be easily removed, leaving almost no permanent damage. Consequently, the procedure of the present invention is a non-destructive method of performing 100% screening of integrated circuits for ionizing dose sensitivity.
2.0 BACKGROUND OF INVENTION
Many military and commercial electronic systems may be exposed to nuclear radiation. Military systems would have to withstand such exposure during nuclear warfare, while commercial space systems will experience this exposure if they operate in natural space radiation. This forces designers of such systems to harden them against the adverse effects of radiation exposure.
2.1 TECHNICAL DISCUSSION
It has been shown that the elements of electronic systems that are most sensitive to radiation are integrated circuits (ICs). Consequently, there is great interest in methods for determining the radiation hardness of the ICs to be used in such applications, and assuring that the hardness level, once determined, is maintained during system production and deployment.
2.1.1 Integrated Circuit Technology
The most widely used integrated circuit technology in the world today is one known as CMOS (complementary metal-oxide semiconductor) technology. The most widely used products using CMOS are digital devices, such as memory chips, microprocessors, etc.. Therefore, the following description of the present invention will address digital CMOS ICs, even though the general approach can also be used for CMOS integrated circuits other than digital CMOS ICs.
CMOS technology gets its name from the fact that P-channel Metal-Oxide-Silicon (MOS) transistors and N-channel MOS transistors are used in series in various combinations to implement logic functions. Since, in operation, one of these transistors is turned OFF while the other is turned ON, circuits implemented in such an arrangement dissipate little power, except when they are changing state. This makes this technology interesting in many applications where low power dissipation is important.
FIG. 1
shows a cross sectional view of the PMOS and NMOS transistors that are used in CMOS ICs, with the gate oxide (usually fabricated with SiO
2
) labeled as such, and the field oxide identified as the SiO
2
region.
FIG. 2
is a circuit schematic showing how such transistors would be used in the simplest CMOS circuit, an inverter. (Output buffers, commonly used on digital CMOS ICs, use this circuit configuration.) The PMOS device is shown as Q
2
in this diagram, and the NMOS device is shown as Q
1
.
A critical parameter of both N-channel and P-channel MOS transistors is the threshold voltage, VT. This is the value of the gate voltage at which significant current begins to flow from the source to the drain. This parameter is the single most important quantity in CMOS integrated circuit technology. It is significantly affected by exposure to ionizing radiation, and therefore is important to the understanding to radiation damage effects in CMOS ICs, and to an appreciation of the object of this patent.
2.1.1.1 Ionizing Radiation Damage in Digital CMOS ICs
Ionizing radiation degrades digital CMOS ICs by (1) causing changes in the threshold voltage (V
TN
) of N-channel MOS transistors, decreasing it under some circumstances, and increasing it under others, by (2) causing increases in the threshold voltage of P-channel MOS transistors (V
TP
), and (3) by causing increases in the ON-resistance (R
ON
) of both types of devices. Decreases in V
TN
can lead to increases in operating current and/or inability to switch. Increases in V
TN
and V
TP
can cause reductions in the speed of operation of a circuit and loss of circuit functionality. Increases in device ON-resistance can lead to inability to drive other circuits, either on-chip or off-chip, with resultant loss of functionality.
The part of a CMOS transistor most sensitive to ionizing radiation is the oxide layer, either the gate oxide or the field oxide. When ionizing radiation impinges on an oxide, the energy deposited creates electron/hole pairs. The electrons (conventionally denoted ‘n’) are more mobile than the holes (denoted ‘h’), and are swept out of the oxides in times of the order of a picosecond. In that time, however, some fraction of the electrons and holes recombine. This fraction depends on the applied electrical field and the energy and kind of the radiation, and is small for normal operating conditions.
FIG. 3
shows the processes involved in radiation damage to CMOS ICs, starting with the generation of electron/hole pairs by radiation, the transport of holes through localized states in SiO
2
bulk, the trapping of some of these holes near the Si/SiO
2
interface and the formation of traps at this interface. The first three of these steps are well understood, but the formation of interface traps remains incompletely understood.
Digital CMOS ICs exhibit radiation-induced failure mechanisms attributable to either positive charge liberated by the radiation and trapped in oxide layers, or to negatively charged traps at the silicon dioxide/silicon interface. The former effect is responsible for the decrease in V
TN
and the increase in V
TP
cited above, and for an increase in ON-resistance of both types of devices. The latter is responsible for increases in V
TN
and V
TP
and also for increases in the ON-resistance of both types of devices.
Process (1) in
FIG. 3
illustrates the generation of electron/hole pairs by ionizing radiation. This process, and the initial recombination that accompanies it, determines the yield of radiation generated holes. This process is well understood, and the yield of charge carriers generated by radiation can be calculated once the rate at which the incident particles lose energy is specified.
Process (2) in
FIG. 3
illustrates the dispersive, hopping transport of holes from their point of creation to the vicinity of the Si/SiO
2
interface. The transport of radiation-generated holes through oxides usually takes place under an electrical bias field, and it takes place via “small polarons”. “Small polaron” transport is a temperature-activated process at temperatures above about 160° K, and is not temperature-activated below 160° K. At temperatures below this transition point, holes are ‘self-trapped’ at their point of creation, while at higher temperatures, they travel toward the silicon (for positive gate bias).
Process (3) in
FIG. 3
illustrates the trapping of holes near the Si/SiO
2
interface. Mobile holes eventually encounter a distribution of hole traps that starts at the Si/SiO
2
interface and extend a few nano-meters into the oxide. Depending on the local density, N
ht
, and hole capture cross section, &sgr;
ht
, of these traps, a fraction f
T
of the holes will be captured. Hole trapping fractions are usually much less than one, so most of the holes drift out of the oxide into the silicon at normal temperatures, and do not contribute to degradation of the electrical properties of devices. Even though f
T
is usually <<1, it can still vary considerably from one device to another. In fact, the magnitude of the hole trapping fraction, f
T
is a parameter that differentiates “hard” oxides from “soft” oxides, with the former usually having f
T
values of <1%, while the latter can have f
T
values of ≈10%. As a result, most holes generated by radiation do not contribute to electrical degradation at room temperature.
Process (4) in
FIG. 3
shows the formation of interface states. The mechanism(s) whereby interface traps are created in CMOS device

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