Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Mesa or stacked emitter
Reexamination Certificate
2002-01-11
2004-01-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Mesa or stacked emitter
C257S571000
Reexamination Certificate
active
06680236
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to GaAs heterojunction bipolar transistors, and, more particularly, to methods of fabricating edge terminations in such devices.
BACKGROUND ART
The performance of semiconductor devices, such as those that consist of layers of different conductivity type semiconductors disposed on top of each other, depends on edges of the device. Properties of the edge are typically different from the bulk of the device and as such usually produce undesirable effects. One example of such undesirable effects is edge breakdown of a reverse biased p-n junction, for example in a diode or a bipolar transistor. The local electric field at the edge of the junction can be much higher than that in the bulk of the junction and acts to degrade the maximum voltage capability of the device.
For a semiconductor such as GaAs, the edge of the termination is thought to degrade the breakdown voltage of the device significantly. It is desirable therefore to find a technique where the field at the edge can be reduced.
Some of the prior art that is improved upon is described in the following publication: F. Ren et al, “Implant isolation of GaAs—AlGaAs heterojunction bipolar transistor structures”,
Applied Physics Letters
, Vol. 56, No. 9, pp. 860-862(Feb. 26, 1990).
Ren et al describe the use of ion-implantation damage for edge termination in heterojunction bipolar transistors (HBTs). Ion-implantation is widely used in MESFETs (metal-semiconductor field effect transistors) and HEMTs (high electron or hole mobility transistors) where the layers to be terminated are relatively shallow; however, ion-implantation becomes less feasible where thick layers of semiconductors are to be isolated. Also, the use of implantation alone is not sufficient for making edge termination devices where highly doped layers are present, such as the HBTs, and the device is expected to withstand high voltages.
Mesa processing is well-known in the technical literature and any text book discussion on HBTs provides sufficient information.
Presently, the edge termination is made by first masking the device and then etching-down semiconductor material around the device, resulting in a mesa structure about 2 to 3 micrometers high. The breakdown voltage in the non-passivated device can be a sensitive function of mesa-depth as well as the edge properties. As such, there is a large variation in breakdown voltage for devices fabricated across a substrate. The breakdown voltage is sensitive to contaminants and easily degrades.
Thus, there is a need to provide a method for improving the edge terminations in such devices while maintaining breakdown voltage at desirable high levels.
DISCLOSURE OF INVENTION
In accordance with the present invention, a method is provided for improving edge terminations in a semiconductor device while maintaining breakdown voltage of said semiconductor device at or near its theoretical limit. The method comprises: employing ion-implantation to create a compensated region around said semiconductor device, followed by wet chemical etching to form a mesa on the order of 0.2 to 0.3 &mgr;m.
The present invention provides a simple but novel method of fabricating edge terminations in semiconductor devices in general and in devices employing p-n junctions such as in a GaAs heterojunction bipolar transistor (HBT) to achieve near-ideal electrical characteristics at the device edge. Instead of traditional edge beveling techniques such as those involving grinding, sandblasting, or mesa-etching using masks, the technique of the present invention utilizes ion-implantation to create a compensated region around the device and wet chemical etching to make a shallow mesa.
A vertical mesa is considered to be the most effective mesa termination in these devices. Where passivation of exposed edges and planarity of the device is considered an issue, ion-implantation has been employed to achieve good device termination. In power HBTs involving collector thickness of many micrometers, either of the two approaches is not satisfactory. The present invention provides a technique that is vital to high-voltage HBTs and could in principle be applied to any HBT device to achieve effective edge termination. By “high-voltage” is meant voltage greater than 100 V, preferably 200 to 700 V, although lower voltage devices, down to 30 V, may also be beneficially improved in accordance with the teachings herein. By “effective edge termination” is meant an edge termination where the properties of the device edges do not limit the operating voltage. In an effectively terminated device, the operating voltage is determined by the properties of the “bulk” of the device.
The purpose of the present invention is to make edge terminations on high voltage HBT devices without degrading the breakdown voltage. A secondary but important purpose is to preserve the planarity of the device. The breakdown voltage of these devices is presently limited by the properties of the edge and the mesa process results in a non-planar device that is difficult to passivate.
With the technique disclosed herein, it is possible to make devices with breakdown voltages very close to the theoretical maximum. This is done without needing a deep mesa on the order of 2 to 3 &mgr;m. In the best devices measured so far, a mesa depth of 0.2 to 0.3 micrometers was sufficient to reach the maximum voltage breakdown. The breakdown voltage remains stable after subsequent processing steps. The edge of the mesa may then be encapsulated using a silicon nitride film.
The teachings of the present invention are applicable to high voltage switching transistors. This device is the enabling technology for VHF power converters, but can be used in many other types of power converters.
In general, the present invention is applicable to all semiconductor devices where edge terminations such as described here may be required.
REFERENCES:
patent: 4599118 (1986-07-01), Han et al.
patent: 5028549 (1991-07-01), Chang et al.
F. Ren et al., “Implant isolation of GaAs-AlGaAs heterojunction bipolar transistor structures”, Applied Physics Letters, vol. 56, No. 9, pp. 860-862 (Feb. 26, 1990).
Appl. Phys. Letters 56 (9), Feb. 26, 1990, “Implant Isolation of GaAs-AlGaAs Heterojunction Bipolar Transistor Structures”.
Hussain Tahir
Montes Mary C.
Alkov Leonard A.
Lenzen, Jr. Glenn H.
Nelms David
Raytheon Company
Vu David
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