Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2011-08-02
2011-08-02
Ngo, Chuong D (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S524000
Reexamination Certificate
active
07991816
ABSTRACT:
A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.
REFERENCES:
patent: 5796644 (1998-08-01), Jiang
patent: 6519621 (2003-02-01), Yano
patent: 2006/0129623 (2006-06-01), Uesugi
patent: 2006/0174094 (2006-08-01), Lloyd et al.
Curran Brian William
Goyal Ashutosh
Vaden Michael Thomas
Webber David Allan
International Business Machines - Corporation
Musgrove Jack V.
Ngo Chuong D
Talpis Matthew B.
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