Inverter output circuit

Details Inverter output circuit Inverter output circuit

2002-10-29

2003-12-16

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S333000, C327S276000, C327S262000

Reexamination Certificate

active

06664823

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to an inverter output circuit for driving a load such as a light emitting diode (LED) and a liquid crystal display (LCD).
BACKGROUND OF THE INVENTION
FIG. 1
shows a circuit having a conventional inverter output circuit for driving an LED. This circuit includes a NAND circuit and serially connected first through third inverters INV
1
-INV
3
, respectively, for outputting a power to control ON/OFF operation of the LED.
The NAND circuit includes a pair of P-type MOS transistors P
1
and P
2
connected in parallel with each other and a pair of N-type MOS transistors N
1
and N
2
connected in series with each other and with the paired MOS transistors P
1
and P
2
. The first through third inverters INV
1
-INV
3
each consist of a P-type MOS transistor (P
11
-P
31
) and an N-type MOS transistor (N
11
-N
31
). A supply voltage of Vdd, with respect to the-ground potential, is provided to the NAND circuit and the inverters INV
1
-INV
3
as the operating voltage thereof.
Referring to
FIG. 2
, operations of the circuit shown in
FIG. 1
will now be discussed below. When the supply voltage Vdd has a normal voltage, the NAND circuit outputs a low level signal (referred to as L-level output) when the NAND circuit receives at the two input terminals thereof high level signals (referred to as H-level inputs), as shown in FIG.
2
(
a
). The L-level output is inverted in sequence in the first through third inverters INV
1
-INV
3
, finally providing a H-level signal (referred to as H-level output). This H-level output will turn OFF the LED. On the other hand, when the NAND circuit receives at its input terminals other signals (i.e. signals of H- and L-inputs, L- and H-inputs, and L-level inputs), the diode LED will be turned ON.
In this way, the NAND circuit controls the ON/OFF operation of the LED through the inversions of the input signal by the respective inverters INV
1
-INV
3
.
However, if the supply voltage Vdd is gradually lowered on account of, for example, shut down of the supply voltage, the NAND circuit can fail to output a correct signal from the third inverter INV
3
in response to the input signal it receives at the input terminals. In what follows, the condition of the inverter circuit in which the circuit can provide a correct output will be referred to as ON status, and otherwise the condition referred to as OFF status.
As shown in
FIG. 1
, the NAND circuit usually contains more transistors than inverters INV
1
-INV
3
and hence requires a higher source-drain voltage than the inverters. Because of this, as the supply voltage Vdd lowers from the nominal level, the NAND circuit is turned OFF at a voltage which is still higher than the turn-off voltage of the inverters INV
1
-INV
3
, and the output of the NAND circuit is fixed to either the H-level or the L-level.
FIG.
2
(
b
) shows such condition as discussed above. Suppose now that the supply voltage Vdd has lowered from the nominal voltage to a certain lower level Vdd
1
causing the NAND circuit to fall into the OFF status, irrespective of whether or not both the input signals have H-level or not, resulting in a H-level output. In this case, the H-level output will be inverted by the enabled inverters INV
1
-INV
3
in sequence, with the third inverter INV
3
generating L-level output. As a result, the LED will be turned ON by the L-level output.
As the supply voltage Vdd further lowers to a level Vdd
2
say, where Vdd
1
>Vdd
2
, all the inverters will fall in the OFF status, thereby turning OFF the LED.
Thus, the LED that has been turned OFF will be turned ON once again for a while as the supply voltage Vdd lowers from the nominal level to a sufficiently low level.
Moreover, when the supply voltage Vdd is lower than the nominal voltage for some reason, the NAND circuit and each of the inverters INV
1
-INV
3
can behave inconsistently based on their operational conditions, resulting in erratic operations of the LED.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to provide an inverter output circuit for correctly driving a load in response to a given input signal if the supply voltage is shut down or lowered.
In one aspect of the invention, there is provided an inverter output circuit, comprising:
a first inverter impressed by a supply voltage given by the difference between a first (high) level potential of a first power supply and a second (low) potential of a second power supply, said first inverter adapted to generate, in accordance with the level of an input signal fed, either
a high level output which equals the high potential of said first power supply, or
a low level (L-level) offset output which is higher than said second potential of said second power supply by a predetermined offset voltage; and
a second inverter impressed by said supply voltage and receiving the output of said first inverter, said second inverter adapted to output either said high level output or a low level output in accordance with the level of the output received, wherein
the input threshold voltage of said second inverter is set up at a higher level than said L-level offset output when said supply voltage is higher than a predetermined reference voltage, and otherwise set up at a lower level than said L-level offset output.
In accordance with an inverter output circuit of the invention, the input threshold voltage Vth
2
of the second inverter INV
2
becomes lower than the L-level offset output Voff of the first inverter INV
1
when the supply voltage Vdd has lowered below the nominal level, and thus the subsequent inverters (including the second inverter INV
2
) will assume correct ON/OFF status to maintain the load turned off.


REFERENCES:
patent: 5068553 (1991-11-01), Love
patent: 5467044 (1995-11-01), Ashe et al.
patent: 5994937 (1999-11-01), Hara et al.
patent: 6034557 (2000-03-01), Schultz et al.

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