Inverter non-volatile memory cell and array system

Details Inverter non-volatile memory cell and array system Inverter non-volatile memory cell and array system

2007-08-14

2007-08-14

Yoha, Connie C. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290, C365S185260, C365S185170, C365S185050

Reexamination Certificate

active

11084214

ABSTRACT:
NVM arrays include rows and columns of NVM cells comprising a floating gate, dual transistor, inverter storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

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