Inverter for use in binary counter

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307453, 307468, 307246, 307262, 377 41, H03K 3356

Patent

active

046804820

ABSTRACT:
An inverter for use in a binary counter comprises a flip-flop having first and second input/output nodes respectively applied with input signals of opposite polarities, a first field effect transistor having a source-drain path connected between the first input/output node and a third node and a gate connected to receive a control clock signal, and a capacitor connected to the third node so as to hold the potential on the first input/output node when the first transistor is turned on. Further, there is provided a switch circuit connected between a supply voltage and a ground and having a first input connected to the third node, a second input connected to receive an inversion control signal, and an output connected to the first input/output node. This switch circuit is responsive to the inversion control signal so as to bring its output to a voltage condition opposite to that held in the capacitor.

REFERENCES:
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patent: 4066874 (1978-01-01), Shaw
patent: 4181862 (1980-01-01), Dingwall
patent: 4361769 (1982-11-01), Hatchett et al.
patent: 4414547 (1983-11-01), Knapp et al.
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patent: 4539495 (1985-09-01), Demler
patent: 4634890 (1987-01-01), Lee
Houdek, "Complementing Up-Down Counter", IBM T.D.B., vol. 13, No. 1, Jun. 1970, p. 290.
Schuster, "JK Latch Using Capacitor Store", IBM T.D.B., vol. 17, No. 6, Nov. 1974, pp. 1824-1825.
Lee, "Race-Free Level Sensitive Master-Slave Latch Utilizing A Single Phase Clock", IBM T. D. B., vol. 20, No. 1, Jun. 1977, pp. 263-264.

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