Inverter device driving method

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver

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Details

327427, H03B 100, H03K 17687

Patent

active

061475246

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The present invention relates to a method for driving an inverter device.
FIG. 1 is a diagram showing a prior known drive circuit of an inverter circuit, wherein this circuit is configured including a first direct current (DC) power supply 1, a upper semiconductor switching element 2 connected to a positive polarity side of the first DC power supply 1, a second drive circuit 4 for turn-on/off drive of the upper switching element 2, and a capacitor 7 for supplying a drive voltage to the drive circuit 4 when this capacitor 7 is charged. This circuit configuration is generally known as the "bootstrap" circuit. During the turn-on period of a lower semiconductor switching element 3 connected to a negative polarity side of the first DC power supply 1, a voltage at an output terminal of FIG. 1 becomes substantially equal to a voltage on the negative side of the first DC power supply 1 so that a circuit for charging and supplying electrical charge to the capacitor 7 from a second DC power supply 6, which is a drive power supply of a first drive circuit 5 for on/off-driving the lower semiconductor switching element 3 connected to the negative polarity side, is provided via a route indicated by dotted line portions in FIG. 1.
The final charge-up voltage being charged by this circuit at the capacitor 7 becomes nearly equal to the voltage of the second DC power supply 6 thereby enabling this capacitor 7 to be directly used as a drive power supply of the second drive circuit 4 which causes the upper semiconductor switching element 2 coupled to the positive polarity side to turn on and off.
Next, one exemplary prior art in the aforementioned configuration is shown in FIG. 2.
The circuit shown in FIG. 2 is designed such that a voltage monitoring circuit 9 is provided for monitoring a voltage between both terminals of the capacitor 7 while also providing an operation function of protecting the upper semiconductor switching element 2 by preventing turn-on of the upper semiconductor switching element 2 connected to the positive polarity side in cases where the capacitor 7 is low in voltage potential, thus eliminating thermal destruction or breakdown otherwise occurring due to turn-on of the upper semiconductor switching element 2 which operates in the state that the drive voltage is kept low in potential (Published Unexamined Japanese Patent Application or "PUJPA" No. 3-150075).
Incidentally, in most cases, it will hardly occur during normal operations that the charged voltage of the capacitor 7 in FIG. 2 becomes lower then a voltage value as set at the voltage monitoring circuit 9, except that this occurs exclusively at a specific time when the capacitor 7 undergoes an initial charge-up at the beginning of start-up of an inverter operation in the inverter device.
Under the features stated above, further in the inverter device, with regard to a means for transferring turn-on/off drive signals to an on/off drive circuit of an upper arm-side semiconductor switching element, another problem occurs in the case where the device employs an on/off signal edge transfer/latch scheme using a drive signal transfer section 12 for use with the upper arm-side semiconductor switching element which section contains therein a high breakdown voltage IC 11 as shown in FIG. 3, rather than continuous signal transfer schemes based on the turn-on/off of a photo-coupler that has been traditionally employed as electrical insulation means, as will be discussed below.
Upon startup of the inverter operation of the inverter device, a lower arm-side semiconductor switching element is typically held in the turn-on state continuously for along time period in order to increase the charge up speed of the capacitor 7. On the other hand, in view of the fact that the turn-on/off signal transmission of the upper arm-side semiconductor switching element follows the edge transfer/latch scheme, where the turn-on signal is accidentally latched during this initial charge up period due to malfunction of the upper arm-side semiconductor sw

REFERENCES:
patent: 5543740 (1996-08-01), Wong
patent: 5963066 (1999-10-01), Fukunaga

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