Inverter circuit

Details Inverter circuit Inverter circuit

1988-10-25

1990-04-10

Karlsen, Ernest F.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

307263, 307542, 307577, G01R 3128, H03K 1900

Patent

active

049163850

ABSTRACT:
An inverter circuit (I.sub.3) is disclosed which includes a P-channel MOSFET (3) and a N-channel MOSFET (4) connected in series between a power supply (V.sub.DD) and a ground (GND). The inverter circuit further includes a P-channel MOSFET (5) and a N-channel MOSFET (6) connected in parallel between the gates of the FETs (3) and (4). The FETs (3) and (4) have their gates connected to receive testing mode signals (T.sub.E). In a testing mode operation, the FET (6) is rendered conductive to allow an input signal to be applied to the gate of the FET (4) through the FET (6). The FET (4), having an on-resistance lower than the FET (3), is driven into conduction in response to the output signal applied through the FET (6), thereby providing a slowly rising output signal. The slow rising output signal is free from undershoot or ringing.

REFERENCES:
patent: 4421994 (1983-12-01), Puri et al.
patent: 4477741 (1984-10-01), Moser, Jr.
patent: 4479067 (1984-10-01), Fujita
patent: 4760279 (1988-07-01), Saito et al.
patent: 4777389 (1988-10-01), Wu et al.
patent: 4782252 (1988-11-01), Levy et al.
patent: 4803383 (1989-02-01), Hirochi
patent: 4820942 (1989-04-01), Chan
Tony Wong et al., "A High Performance 129K Gate CMOS Array" IEEE 1986 Custom Integrated Circuits Conference, pp. 568-571.

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