Inverter circuit

Details Inverter circuit Inverter circuit

2003-04-14

2004-06-01

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S112000, C327S328000, C327S312000, C326S121000, C326S122000

Reexamination Certificate

active

06744297

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an inverter circuit, and more particularly to an inverter circuit for use in an integrated circuit (IC).
BACKGROUND OF THE INVENTION
Please refer to
FIG. 1
which is a circuit diagram showing a conventional complementary metal-oxide-semiconductor (CMOS) inverter. The CMOS inverter includes an N-channel metal-oxide semiconductor (NMOS) transistor
11
and a P-channel metal-oxide semiconductor (PMOS) transistor
12
. When an input signal is a perfect bi-level signal, for example having a low level of 0 V and a high level of 2.5 V, the current is generated only at the transition state other than the steady state.
However, the input signal is not always perfect. When the low level of the input signal is far from the perfect 0 V, e.g. 0.75 or even 0.9 V, the NMOS transistor
12
will be slightly turned on, resulting in the current leakage. Thus, the power consumption of the CMOS inverter largely increases.
Therefore, the purpose of the present invention is to develop an inverter circuit for use in an integrated circuit to deal with the above situations encountered in the prior art.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an inverter circuit for efficiently preventing the current leakage from occurrence and decreasing the power consumption.
According to an aspect of the present invention, there is provided an inverter circuit includes an input end receiving an input signal having a low level and a high level, wherein the low level is greater than zero, a P-channel metal-oxide-semiconductor (PMOS) transistor having a gate electrode coupled to the input end and a source electrode coupled to a voltage source, a first N-channel metal-oxide-semiconductor (NMOS) transistor having a drain electrode coupled to a drain electrode of the PMOS transistor to serve as an output end, and a source electrode thereof coupled to ground, and a voltage drop device coupled to the gate electrode of the first NMOS transistor and the input end to provide a voltage drop from the input end to the gate electrode of the first NMOS transistor, thereby eliminating a current leakage of the first NMOS transistor at the low level of the input signal.
In an embodiment, the voltage drop device is a diode having an anode coupled to the input end, and a cathode commonly coupled to ground with the gate electrode of the first NMOS transistor. Preferably, the diode is implemented by a second NMOS transistor having a gate electrode and a drain electrode commonly coupled to the input end, and a source electrode commonly coupled to ground with the gate electrode of the first NMOS transistor. Preferably, the source electrode of the second NMOS transistor and the gate electrode of the first NMOS transistor are coupled to ground via a third NMOS transistor. The third NMOS transistor has a drain electrode coupled to the source electrode of the second NMOS transistor and the gate electrode of the first NMOS transistor. A source electrode of the third NMOS transistor is coupled to ground, and a gate electrode of the third NMOS transistor is coupled to the output end.
In an embodiment, the inverter circuit further includes a fourth NMOS transistor and a fifth NMOS transistor. The fourth NMOS transistor has a drain electrode and a source electrode connected to the source electrode of the second NMOS transistor and the drain electrode of the third NMOS transistor in series, respectively. A gate electrode of the fourth NMOS transistor is coupled to the input end. The fifth NMOS transistor has a gate electrode coupled to both the drain electrode of the fourth NMOS transistor and the source electrode of the second NMOS transistor. A drain electrode and a source electrode of the fifth NMOS transistor are coupled to the output end and ground, respectively. Preferably, the second and fourth NMOS transistors are substantially of the same size. Preferably, the first NMOS transistor has a channel wider than a channel of the fifth NMOS transistor.
For example, the low level lies between about 0.7 and about 0.9 V, and the high level is about 2.5 V.


REFERENCES:
patent: 4490633 (1984-12-01), Noufer et al.
patent: 4617482 (1986-10-01), Matsuda
patent: 5066930 (1991-11-01), Morse
patent: 5149991 (1992-09-01), Rogers
patent: 6617903 (2003-09-01), Kawamura

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