Inverted spacer transistor

Details Inverted spacer transistor Inverted spacer transistor

1994-08-10

1995-07-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 40, 437 44, 437 45, 437984, H01L 21265

Patent

active

054340934

ABSTRACT:
A method for forming narrow length transistors by forming a trench in a first layer over a semiconductor substrate. Spacers are then formed within the trench and a gate dielectric is formed between the spacers at the bottom of the trench on the semiconductor substrate. The trench is then filled with a gate electrode material which is chemically-mechanically polished back to isolate the gate electrode material within the trench, and the first layer is removed leaving the gate dielectric, gate electrode and spacers behind.

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"A Fully Planarized C.25 .mu.m CMOS Technology", D. S. Wen, W. H. Chang, Y, Lii, A. C. Megdanis, P. McFarland and G. B. Bonner, VLSI, 1992.
"A Sub-0.1-.mu.m Groved Gate MOSFET with High Immunity to Short-Channel Effects", Junko Tanka, Shin'ichiro Kimura, Hiromasa Noda, Toru Toyabe and Sigeo Ihara, IEEE, 1993.
"A 0.1 .mu.m-gate Elevated Source and Drain MOSFET fabricated by Phase-shifted Lithography", Shin'ichiro Kimura, Hiromasa Noda, Digh Hisamoto and Eiji Takeda, IEDM, 1991.

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