Inverse T-gate semiconductor device with self-aligned punchthrou

Details Inverse T-gate semiconductor device with self-aligned punchthrou Inverse T-gate semiconductor device with self-aligned punchthrou

1996-02-16

1996-12-10

Picardat, Kevin

Fishing, trapping, and vermin destroying

437405, 437 41, H01L 21265

Patent

active

055830676

ABSTRACT:
A high speed submicron metal-oxide-semiconductor transistor which exhibits a high immunity to hot electron degradation, good performance, and excellent punchthrough characteristics. An inverse T gate comprising an upper member and a lower member is formed on a well of a first conductivity type. A gate insulating layer is formed between the composite gate and the well. A pair of first conductivity type punchthrough stop regions are formed apart in the well in alignment with the laterally opposite sides of the upper gate member. A first oxide sidewall spacer is formed adjacent to laterally opposite sidewalls of the upper gate member on the lower gate member. A first pair of source/drain regions of a second conductivity type are formed in alignment with the first oxide sidewall spacers. A second sidewall spacer is formed adjacent to each of the first sidewall spacers on the lower gate member. A second source and second drain region of the second conductivity type are formed in the first source and first drain regions, respectively. The second source and second drain regions are formed in alignment with the outer edges of the second sidewall spacers.

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