Inverse discrete cosine transform calculation processor

Boots – shoes – and leggings

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G06F 15332

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046791639

ABSTRACT:
An inverse discrete cosine transform calculation processor, for processing television picture signals, comprises a processor module consisting of four successive stages. The first stage comprises a multiplier associated with a sine and cosine function value store which is connected to one of its input buses. Each of the other three stages comprises an adder/subtracter having two input buses each selectively connected to the output bus of the directly preceding stage or to the output bus of an input register of this stage also loaded from the output bus of the directly preceding stage and which features on the output bus of one of the input registers of the fourth stage an internal loopback bus which with an input bus of the module is selectively connected to the second input bus of the multiplier.

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