Invalidation queue with "bit-sliceability"

Details Invalidation queue with "bit-sliceability" Invalidation queue with "bit-sliceability"

1993-07-15

1997-06-24

Chan, Eddie P.

395468, 395872, 395448, 395445, G06F 1208

Patent

active

056424868

ABSTRACT:
An Invalidation Queue (IQ) arrangement in a computer system having Main Memory and, Cache-Memory, with a pair of intermediate main-buses this IQ arrangement comprising: a pair of split IQ ASIC Arrays disposed between each Cache-Memory and the main-buses and being adapted to assure identical data in all identical memory addresses in different caches, and to "remember" write-operations along the buses and to execute invalidation sequences for any Cache-Memory unit as dictated by that Cache-Memory unit.

REFERENCES:
patent: 5226146 (1993-07-01), Milia et al.
patent: 5265232 (1993-11-01), Gannon et al.
patent: 5339399 (1994-08-01), Lee et al.
patent: 5398325 (1995-03-01), Chang et al.

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