Introducing processing delay as a multiple of the time slot dura

Details Introducing processing delay as a multiple of the time slot dura Introducing processing delay as a multiple of the time slot dura

1996-02-27

1999-03-23

Chin, Stephen

Pulse or digital communications

Receivers

Interference or noise reduction

375349, 455562, 455 65, 455303, H04B 706

Patent

active

058870377

ABSTRACT:
An apparatus for performance improvement of a burst mode digital wireless receiver has a processing circuit for processing a plurality of received signals and providing a processed signal and a delay circuit for introducing a predetermined delay to the processed signal. The delay circuit is coupled to the processing circuit. The predetermined delay is such that the processed signal is delayed to correspond with a later data burst. The processing circuit weights and combines the received signals, where the processing circuit reduces a mean squared error of an output signal. The processing circuit weights and combines the received signals using a predetermined symbol pattern within a sync sequence within a time slot.

REFERENCES:
patent: 4397036 (1983-08-01), Hirade et al.
patent: 5481570 (1996-01-01), Winters
patent: 5530725 (1996-06-01), Koch
patent: 5592490 (1997-01-01), Barratt et al.
Winters, J., Signal Acquisitions and Tracking with Adaptive Arrays in the Digital Mobile Radio System IS-54 with Flat Fading; published in IEEE Transactions on Vehicular Technology, vol. 42, No. 4, Nov., 1993, pp. 377-384.
Winters, J., et al The Impact of Antenna Diversity on the Capacity of Wireless Communications Systems, published in IEEE Transactions on Communications, vol. 42, No. 2/3/4, Feb., Mar., Apr., 1994 pp. 1740-1751.

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